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From: Tony Lindgren <tony@atomide.com>
To: Yegor Yefremov <yegor_sub1@visionsystems.de>
Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
	arm-linux <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] GPMC: add ECC control definitions
Date: Mon, 5 Mar 2012 15:03:34 -0800	[thread overview]
Message-ID: <20120305230334.GM12083@atomide.com> (raw)
In-Reply-To: <4F1D4CB3.5080803@visionsystems.de>

* Yegor Yefremov <yegor_sub1@visionsystems.de> [120123 03:33]:
> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> ---
>  arch/arm/mach-omap2/gpmc.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)
> 
> Index: b/arch/arm/mach-omap2/gpmc.c
> ===================================================================
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -50,6 +50,19 @@
>  #define GPMC_ECC_SIZE_CONFIG	0x1fc
>  #define GPMC_ECC1_RESULT        0x200
>  
> +/* GPMC ECC control settings */
> +#define GPMC_ECC_CTRL_ECCCLEAR		0x100
> +#define GPMC_ECC_CTRL_ECCDISABLE	0x000
> +#define GPMC_ECC_CTRL_ECCREG1		0x001
> +#define GPMC_ECC_CTRL_ECCREG2		0x002
> +#define GPMC_ECC_CTRL_ECCREG3		0x003
> +#define GPMC_ECC_CTRL_ECCREG4		0x004
> +#define GPMC_ECC_CTRL_ECCREG5		0x005
> +#define GPMC_ECC_CTRL_ECCREG6		0x006
> +#define GPMC_ECC_CTRL_ECCREG7		0x007
> +#define GPMC_ECC_CTRL_ECCREG8		0x008
> +#define GPMC_ECC_CTRL_ECCREG9		0x009
> +
>  #define GPMC_CS0_OFFSET		0x60
>  #define GPMC_CS_SIZE		0x30
>  
> @@ -855,8 +868,9 @@
>  	gpmc_ecc_used = cs;
>  
>  	/* clear ecc and enable bits */
> -	val = ((0x00000001<<8) | 0x00000001);
> -	gpmc_write_reg(GPMC_ECC_CONTROL, val);
> +	gpmc_write_reg(GPMC_ECC_CONTROL,
> +			GPMC_ECC_CTRL_ECCCLEAR |
> +			GPMC_ECC_CTRL_ECCREG1);
>  
>  	/* program ecc and result sizes */
>  	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
> @@ -864,13 +878,19 @@
>  
>  	switch (mode) {
>  	case GPMC_ECC_READ:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	case GPMC_ECC_READSYN:
> -		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCDISABLE);
>  		break;
>  	case GPMC_ECC_WRITE:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	default:
>  		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
> 

No functional changes here, right?

Can GPMC_ECC_READ and GPMC_ECC_WRITE case be combined:

	switch (mode) {
	case GPMC_ECC_READ:
	case GPMC_ECC_WRITE:
		gpmc_write_reg(GPMC_ECC_CONTROL,
			GPMC_ECC_CTRL_ECCCLEAR |
			GPMC_ECC_CTRL_ECCREG1);
	break;
	...

Regards,

Tony

WARNING: multiple messages have this Message-ID (diff)
From: tony@atomide.com (Tony Lindgren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] GPMC: add ECC control definitions
Date: Mon, 5 Mar 2012 15:03:34 -0800	[thread overview]
Message-ID: <20120305230334.GM12083@atomide.com> (raw)
In-Reply-To: <4F1D4CB3.5080803@visionsystems.de>

* Yegor Yefremov <yegor_sub1@visionsystems.de> [120123 03:33]:
> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> ---
>  arch/arm/mach-omap2/gpmc.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)
> 
> Index: b/arch/arm/mach-omap2/gpmc.c
> ===================================================================
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -50,6 +50,19 @@
>  #define GPMC_ECC_SIZE_CONFIG	0x1fc
>  #define GPMC_ECC1_RESULT        0x200
>  
> +/* GPMC ECC control settings */
> +#define GPMC_ECC_CTRL_ECCCLEAR		0x100
> +#define GPMC_ECC_CTRL_ECCDISABLE	0x000
> +#define GPMC_ECC_CTRL_ECCREG1		0x001
> +#define GPMC_ECC_CTRL_ECCREG2		0x002
> +#define GPMC_ECC_CTRL_ECCREG3		0x003
> +#define GPMC_ECC_CTRL_ECCREG4		0x004
> +#define GPMC_ECC_CTRL_ECCREG5		0x005
> +#define GPMC_ECC_CTRL_ECCREG6		0x006
> +#define GPMC_ECC_CTRL_ECCREG7		0x007
> +#define GPMC_ECC_CTRL_ECCREG8		0x008
> +#define GPMC_ECC_CTRL_ECCREG9		0x009
> +
>  #define GPMC_CS0_OFFSET		0x60
>  #define GPMC_CS_SIZE		0x30
>  
> @@ -855,8 +868,9 @@
>  	gpmc_ecc_used = cs;
>  
>  	/* clear ecc and enable bits */
> -	val = ((0x00000001<<8) | 0x00000001);
> -	gpmc_write_reg(GPMC_ECC_CONTROL, val);
> +	gpmc_write_reg(GPMC_ECC_CONTROL,
> +			GPMC_ECC_CTRL_ECCCLEAR |
> +			GPMC_ECC_CTRL_ECCREG1);
>  
>  	/* program ecc and result sizes */
>  	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
> @@ -864,13 +878,19 @@
>  
>  	switch (mode) {
>  	case GPMC_ECC_READ:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	case GPMC_ECC_READSYN:
> -		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCDISABLE);
>  		break;
>  	case GPMC_ECC_WRITE:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	default:
>  		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
> 

No functional changes here, right?

Can GPMC_ECC_READ and GPMC_ECC_WRITE case be combined:

	switch (mode) {
	case GPMC_ECC_READ:
	case GPMC_ECC_WRITE:
		gpmc_write_reg(GPMC_ECC_CONTROL,
			GPMC_ECC_CTRL_ECCCLEAR |
			GPMC_ECC_CTRL_ECCREG1);
	break;
	...

Regards,

Tony

  reply	other threads:[~2012-03-05 23:03 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-01-23 12:04 [PATCH] GPMC: add ECC control definitions Yegor Yefremov
2012-01-23 12:04 ` Yegor Yefremov
2012-03-05 23:03 ` Tony Lindgren [this message]
2012-03-05 23:03   ` Tony Lindgren
2012-03-08 11:10   ` Yegor Yefremov
2012-03-08 11:10     ` Yegor Yefremov

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