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From: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
To: Tomoya MORINAGA
	<tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	Tomoya MORINAGA
	<tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	kok.howg.ewe-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	joel.clark-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH 3/4][RESEND] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
Date: Fri, 09 Mar 2012 20:57:41 -0700	[thread overview]
Message-ID: <20120310035741.F39203E06B6@localhost> (raw)
In-Reply-To: <1323404009-3476-2-git-send-email-tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri,  9 Dec 2011 13:13:28 +0900, Tomoya MORINAGA <tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> This patch supports a spi mode setup and bit order setup by IO control.
>     spi mode:     mode 0 to mode 3
>     bit order:    LSB first, MSB first
> 
> Signed-off-by: Tomoya MORINAGA <tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Applied, thanks.

g.

> ---
>  drivers/spi/spi-topcliff-pch.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
> index 7339765..1864555 100644
> --- a/drivers/spi/spi-topcliff-pch.c
> +++ b/drivers/spi/spi-topcliff-pch.c
> @@ -1430,6 +1430,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
>  	master->num_chipselect = PCH_MAX_CS;
>  	master->setup = pch_spi_setup;
>  	master->transfer = pch_spi_transfer;
> +	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
>  
>  	data->board_dat = board_dat;
>  	data->plat_dev = plat_dev;
> -- 
> 1.7.4.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.

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WARNING: multiple messages have this Message-ID (diff)
From: Grant Likely <grant.likely@secretlab.ca>
To: Tomoya MORINAGA <tomoya.rohm@gmail.com>,
	spi-devel-general@lists.sourceforge.net,
	linux-kernel@vger.kernel.org
Cc: qi.wang@intel.com, yong.y.wang@intel.com, joel.clark@intel.com,
	kok.howg.ewe@intel.com, Wolfram Sang <w.sang@pengutronix.de>,
	Tomoya MORINAGA <tomoya.rohm@gmail.com>
Subject: Re: [PATCH 3/4][RESEND] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
Date: Fri, 09 Mar 2012 20:57:41 -0700	[thread overview]
Message-ID: <20120310035741.F39203E06B6@localhost> (raw)
In-Reply-To: <1323404009-3476-2-git-send-email-tomoya.rohm@gmail.com>

On Fri,  9 Dec 2011 13:13:28 +0900, Tomoya MORINAGA <tomoya.rohm@gmail.com> wrote:
> This patch supports a spi mode setup and bit order setup by IO control.
>     spi mode:     mode 0 to mode 3
>     bit order:    LSB first, MSB first
> 
> Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>

Applied, thanks.

g.

> ---
>  drivers/spi/spi-topcliff-pch.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
> index 7339765..1864555 100644
> --- a/drivers/spi/spi-topcliff-pch.c
> +++ b/drivers/spi/spi-topcliff-pch.c
> @@ -1430,6 +1430,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
>  	master->num_chipselect = PCH_MAX_CS;
>  	master->setup = pch_spi_setup;
>  	master->transfer = pch_spi_transfer;
> +	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
>  
>  	data->board_dat = board_dat;
>  	data->plat_dev = plat_dev;
> -- 
> 1.7.4.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.

  parent reply	other threads:[~2012-03-10  3:57 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-12-09  4:13 [PATCH 2/4] spi-topcliff-pch: Fix issue for transmitting over 4KByte Tomoya MORINAGA
2011-12-09  4:13 ` Tomoya MORINAGA
     [not found] ` <1323404009-3476-1-git-send-email-tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-12-09  4:13   ` [PATCH 3/4][RESEND] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control Tomoya MORINAGA
2011-12-09  4:13     ` Tomoya MORINAGA
     [not found]     ` <1323404009-3476-2-git-send-email-tomoya.rohm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-10  3:57       ` Grant Likely [this message]
2012-03-10  3:57         ` Grant Likely
2011-12-09  4:13   ` [PATCH 4/4] spi-topcliff-pch: add recovery processing in case wait-event timeout Tomoya MORINAGA
2011-12-09  4:13     ` Tomoya MORINAGA
2012-03-10  3:58     ` Grant Likely
2012-03-10  3:56   ` [PATCH 2/4] spi-topcliff-pch: Fix issue for transmitting over 4KByte Grant Likely
2012-03-10  3:56     ` Grant Likely

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