From: Mike Frysinger <vapier@gentoo.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines
Date: Wed, 25 Apr 2012 18:54:40 -0400 [thread overview]
Message-ID: <201204251854.41947.vapier@gentoo.org> (raw)
In-Reply-To: <1335254024-30115-2-git-send-email-thierry.reding@avionic-design.de>
On Tuesday 24 April 2012 03:53:44 Thierry Reding wrote:
> The MMC core sometimes reads buffers that are smaller than a complete
> cacheline, for example when reading the SCR. In order to avoid a warning
> from the ARM v7 cache handling code, this patch makes sure that complete
> cachelines are flushed.
this is still wrong. all you've done is bypass the error message without
addressing the underlying problem -- you're invalidating too much.
-mike
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next prev parent reply other threads:[~2012-04-25 22:54 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-24 7:53 [U-Boot] [PATCH 1/2] part_dos: allocate cacheline aligned buffers Thierry Reding
2012-04-24 7:53 ` [U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines Thierry Reding
2012-04-25 22:54 ` Mike Frysinger [this message]
2012-04-26 6:18 ` Thierry Reding
2012-04-26 10:16 ` Simon Glass
2012-04-26 10:34 ` Thierry Reding
2012-04-27 5:29 ` Mike Frysinger
2012-04-27 5:50 ` Simon Glass
2012-11-02 20:22 ` Stephen Warren
2012-11-02 20:25 ` Simon Glass
2012-11-02 20:38 ` Marek Vasut
2012-11-02 20:58 ` Stephen Warren
2012-11-02 21:28 ` Marek Vasut
2012-11-02 21:31 ` Stephen Warren
2012-11-02 22:10 ` Marek Vasut
2012-11-05 19:50 ` Stephen Warren
2012-11-05 22:59 ` Marek Vasut
2012-11-05 23:07 ` Simon Glass
2012-11-02 20:55 ` Stephen Warren
2012-04-24 18:31 ` [U-Boot] [PATCH 1/2] part_dos: allocate cacheline aligned buffers Simon Glass
2012-04-24 18:45 ` Thierry Reding
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