From: Catalin Marinas <catalin.marinas@arm.com>
To: shiraz hashim <shiraz.linux.kernel@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>,
"linux-samsung-soc@vger.kernel.org"
<linux-samsung-soc@vger.kernel.org>,
"ben-linux@fluff.org" <ben-linux@fluff.org>,
Russell King <rmk+kernel@arm.linux.org.uk>,
Changhwan Youn <chaos.youn@samsung.com>,
"stable@kernel.org" <stable@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
Date: Mon, 13 Aug 2012 08:39:44 +0100 [thread overview]
Message-ID: <20120813073944.GA13508@arm.com> (raw)
In-Reply-To: <CAPub14_9vNoiOMEeBDSkJo6NQaazcNvAYu8oD_E2ReEYLfrX+A@mail.gmail.com>
On Mon, Aug 13, 2012 at 08:21:14AM +0100, shiraz hashim wrote:
> On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> >
> > On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > > --- a/arch/arm/mach-s5pv310/cpu.c
> > > +++ b/arch/arm/mach-s5pv310/cpu.c
> > > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> > > __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> > > S5P_VA_L2CC + L2X0_POWER_CTRL);
> > >
> > > - l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > > + l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
> >
> > The patch is fine.
> >
> > But I think we should also set this bit in the cache-l2x0.c file if
> > PL310. That's such a fundamental issue and it's easy to miss in the
> > platform code.
>
> Sorry for reviving this old patch but any reasons why it didn't
> go to the cache-l2x0.c directly (for PL310).
The cache-l2x0.c patch has been around for a while:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1
It may no longer apply cleanly but I haven't revived it since it wasn't
accepted at the time.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
Date: Mon, 13 Aug 2012 08:39:44 +0100 [thread overview]
Message-ID: <20120813073944.GA13508@arm.com> (raw)
In-Reply-To: <CAPub14_9vNoiOMEeBDSkJo6NQaazcNvAYu8oD_E2ReEYLfrX+A@mail.gmail.com>
On Mon, Aug 13, 2012 at 08:21:14AM +0100, shiraz hashim wrote:
> On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> >
> > On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > > --- a/arch/arm/mach-s5pv310/cpu.c
> > > +++ b/arch/arm/mach-s5pv310/cpu.c
> > > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> > > __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> > > S5P_VA_L2CC + L2X0_POWER_CTRL);
> > >
> > > - l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > > + l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
> >
> > The patch is fine.
> >
> > But I think we should also set this bit in the cache-l2x0.c file if
> > PL310. That's such a fundamental issue and it's easy to miss in the
> > platform code.
>
> Sorry for reviving this old patch but any reasons why it didn't
> go to the cache-l2x0.c directly (for PL310).
The cache-l2x0.c patch has been around for a while:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1
It may no longer apply cleanly but I haven't revived it since it wasn't
accepted at the time.
--
Catalin
next prev parent reply other threads:[~2012-08-13 7:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-17 6:55 [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register Kukjin Kim
2010-11-17 6:55 ` Kukjin Kim
2010-11-17 9:07 ` Catalin Marinas
2010-11-17 9:07 ` Catalin Marinas
2012-08-13 7:21 ` shiraz hashim
2012-08-13 7:21 ` shiraz hashim
2012-08-13 7:39 ` Catalin Marinas [this message]
2012-08-13 7:39 ` Catalin Marinas
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