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* [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc
@ 2012-09-12 22:28 Franck Jullien
  2012-09-12 22:28 ` [PATCH 2/3] Add OpenRISC Image type Franck Jullien
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Franck Jullien @ 2012-09-12 22:28 UTC (permalink / raw)
  To: barebox

In a previous patch, Sascha needed to add __ashrdi3 and then linked
to libgcc. This patch add the ashrdi3 function in the arch/openrisc/lib
directory and remove the libgcc dependency.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 arch/openrisc/Makefile      |    4 ---
 arch/openrisc/lib/Makefile  |    1 +
 arch/openrisc/lib/ashrdi3.S |   59 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 4 deletions(-)
 create mode 100644 arch/openrisc/lib/ashrdi3.S

diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
index 1f4b175..fd8bbbf 100644
--- a/arch/openrisc/Makefile
+++ b/arch/openrisc/Makefile
@@ -1,7 +1,5 @@
 CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
 
-LIBGCC          := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
-
 board-$(CONFIG_GENERIC) := generic
 
 KALLSYMS += --symbol-prefix=_
@@ -20,6 +18,4 @@ common-y += $(BOARD)
 common-y += arch/openrisc/lib/
 common-y += arch/openrisc/cpu/
 
-common-y          += $(LIBGCC)
-
 lds-y += arch/openrisc/cpu/barebox.lds
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index aaf93cb..0b3cc50 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -4,3 +4,4 @@ obj-y                 += cpuinfo.o
 obj-y                 += muldi3.o
 obj-y                 += lshrdi3.o
 obj-y                 += ashldi3.o
+obj-y                 += ashrdi3.o
diff --git a/arch/openrisc/lib/ashrdi3.S b/arch/openrisc/lib/ashrdi3.S
new file mode 100644
index 0000000..c656d9f
--- /dev/null
+++ b/arch/openrisc/lib/ashrdi3.S
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2012 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * Extracted from gcc generated assembly.
+ *
+ * Extended precision shifts.
+ *
+ * R3/R4 (MSW, LSW) has 64 bit value
+ * R5    has shift count
+ * result in R11/R12
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+.globl __ashrdi3
+
+__ashrdi3:
+	l.sfeqi r5,0x0			/* if count = 0, go out                   */
+	l.bf out
+
+	l.addi r6,r0,0x20		/* r6 = 32                                */
+	l.sub r6,r6,r5			/* r6 = 32 - count                        */
+	l.sfgtsi r6,0x0			/* if count >= 32                         */
+	l.bnf more_than_32		/* branch to more_than_32                 */
+	l.nop 0x0
+
+
+ less_than_32:
+	l.sll r6,r3,r6			/* r6 gets the bits moved from MSW to LSW */
+	l.srl r4,r4,r5			/* shift LSW                              */
+	l.sra r5,r3,r5			/* shift MSW to r5                        */
+	l.or r4,r6,r4			/* LSW gets bits shifted from MSW         */
+	l.ori r3,r5,0x0			/* r3 = MSW                               */
+
+ out:
+	l.ori r11,r3,0x0
+	l.jr r9
+	l.ori r12,r4,0x0
+
+ more_than_32:
+	l.srai r5,r3,0x1f		/* r5 = MSW sign extended                 */
+	l.sub r4,r0,r6			/* r4 = -r6, the number of bits above 32  */
+	l.sra r4,r3,r4			/* LSW gets bits shifted from MSB         */
+	l.j out				/* go out                                 */
+	l.ori r3,r5,0x0			/* r3 = MSW                               */
-- 
1.7.1


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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/3] Add OpenRISC Image type
  2012-09-12 22:28 [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Franck Jullien
@ 2012-09-12 22:28 ` Franck Jullien
  2012-09-12 22:28 ` [PATCH 3/3] [MCI_SPI] Fix endianness error on be target Franck Jullien
  2012-09-14  6:40 ` [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Sascha Hauer
  2 siblings, 0 replies; 4+ messages in thread
From: Franck Jullien @ 2012-09-12 22:28 UTC (permalink / raw)
  To: barebox

This patch sync the image type list with the kernel in order to add
openrisc support.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 common/image.c  |    2 ++
 include/image.h |    5 +++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/common/image.c b/common/image.c
index e7d2242..e02fbe6 100644
--- a/common/image.c
+++ b/common/image.c
@@ -61,6 +61,8 @@ static table_entry_t arch_name[] = {
 	{ IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{ IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{ IH_ARCH_AVR32,	"avr32",	"AVR32",	},
+	{ IH_ARCH_NDS32,	"nds32",	"NDS32",	},
+	{ IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
 	{ -1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 027b5f2..5f45b6f 100644
--- a/include/image.h
+++ b/include/image.h
@@ -85,6 +85,9 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_LINUX		18	/* Linux	*/
+#define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
+#define IH_ARCH_NDS32		20	/* ANDES Technology - NDS32  */
+#define IH_ARCH_OPENRISC	21	/* OpenRISC 1000  */
 
 #if defined(__PPC__)
 #define IH_ARCH IH_ARCH_PPC
@@ -102,6 +105,8 @@
 #define IH_ARCH IH_ARCH_MICROBLAZE
 #elif defined(__nios2__)
 #define IH_ARCH IH_ARCH_NIOS2
+#elif defined(__OR1K__)
+#define IH_ARCH IH_ARCH_OPENRISC
 #elif defined(__blackfin__)
 #define IH_ARCH IH_ARCH_BLACKFIN
 #elif defined(__avr32__)
-- 
1.7.1


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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 3/3] [MCI_SPI] Fix endianness error on be target
  2012-09-12 22:28 [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Franck Jullien
  2012-09-12 22:28 ` [PATCH 2/3] Add OpenRISC Image type Franck Jullien
@ 2012-09-12 22:28 ` Franck Jullien
  2012-09-14  6:40 ` [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Sascha Hauer
  2 siblings, 0 replies; 4+ messages in thread
From: Franck Jullien @ 2012-09-12 22:28 UTC (permalink / raw)
  To: barebox

Use be(xx)_to_cpu function to switch endianness intelligently.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 drivers/mci/mci_spi.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mci/mci_spi.c b/drivers/mci/mci_spi.c
index a659ebb..a771052 100644
--- a/drivers/mci/mci_spi.c
+++ b/drivers/mci/mci_spi.c
@@ -181,7 +181,7 @@ static uint mmc_spi_readdata(struct mmc_spi_host *host, void *xbuf,
 			mmc_spi_readbytes(host, bsize, buf);
 			mmc_spi_readbytes(host, 2, &crc);
 #ifdef CONFIG_MMC_SPI_CRC_ON
-			if (swab16(cyg_crc16(buf, bsize)) != crc) {
+			if (be16_to_cpu(cyg_crc16(buf, bsize)) != crc) {
 				dev_dbg(host->dev, "%s: CRC error\n", __func__);
 				r1 = R1_SPI_COM_CRC;
 				break;
@@ -212,7 +212,7 @@ static uint mmc_spi_writedata(struct mmc_spi_host *host, const void *xbuf,
 
 	while (bcnt--) {
 #ifdef CONFIG_MMC_SPI_CRC_ON
-		crc = swab16(cyg_crc16((u8 *)buf, bsize));
+		crc = be16_to_cpu(cyg_crc16((u8 *)buf, bsize));
 #endif
 		mmc_spi_writebytes(host, 2, tok);
 		mmc_spi_writebytes(host, bsize, (void *)buf);
@@ -291,7 +291,7 @@ static int mmc_spi_request(struct mci_host *mci, struct mci_cmd *cmd, struct mci
 	} else if (cmd->resp_type == MMC_RSP_R2) {
 		r1 = mmc_spi_readdata(host, cmd->response, 1, 16);
 		for (i = 0; i < 4; i++)
-			cmd->response[i] = swab32(cmd->response[i]);
+			cmd->response[i] = be32_to_cpu(cmd->response[i]);
 		dev_dbg(host->dev, "MMC_RSP_R2 -> %x %x %x %x\n", cmd->response[0], cmd->response[1],
 		      cmd->response[2], cmd->response[3]);
 	} else if (!data) {
@@ -299,7 +299,7 @@ static int mmc_spi_request(struct mci_host *mci, struct mci_cmd *cmd, struct mci
 		case SD_CMD_SEND_IF_COND:
 		case MMC_CMD_SPI_READ_OCR:
 			mmc_spi_readbytes(host, 4, cmd->response);
-			cmd->response[0] = swab32(cmd->response[0]);
+			cmd->response[0] = be32_to_cpu(cmd->response[0]);
 			break;
 		}
 	} else {
-- 
1.7.1


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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc
  2012-09-12 22:28 [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Franck Jullien
  2012-09-12 22:28 ` [PATCH 2/3] Add OpenRISC Image type Franck Jullien
  2012-09-12 22:28 ` [PATCH 3/3] [MCI_SPI] Fix endianness error on be target Franck Jullien
@ 2012-09-14  6:40 ` Sascha Hauer
  2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2012-09-14  6:40 UTC (permalink / raw)
  To: Franck Jullien; +Cc: barebox

Hi Franck,

On Thu, Sep 13, 2012 at 12:28:32AM +0200, Franck Jullien wrote:
> In a previous patch, Sascha needed to add __ashrdi3 and then linked
> to libgcc. This patch add the ashrdi3 function in the arch/openrisc/lib
> directory and remove the libgcc dependency.
> 
> Signed-off-by: Franck Jullien <franck.jullien@gmail.com>


Applied this series.

Thanks
 Sascha

> ---
>  arch/openrisc/Makefile      |    4 ---
>  arch/openrisc/lib/Makefile  |    1 +
>  arch/openrisc/lib/ashrdi3.S |   59 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 60 insertions(+), 4 deletions(-)
>  create mode 100644 arch/openrisc/lib/ashrdi3.S
> 
> diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
> index 1f4b175..fd8bbbf 100644
> --- a/arch/openrisc/Makefile
> +++ b/arch/openrisc/Makefile
> @@ -1,7 +1,5 @@
>  CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
>  
> -LIBGCC          := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
> -
>  board-$(CONFIG_GENERIC) := generic
>  
>  KALLSYMS += --symbol-prefix=_
> @@ -20,6 +18,4 @@ common-y += $(BOARD)
>  common-y += arch/openrisc/lib/
>  common-y += arch/openrisc/cpu/
>  
> -common-y          += $(LIBGCC)
> -
>  lds-y += arch/openrisc/cpu/barebox.lds
> diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
> index aaf93cb..0b3cc50 100644
> --- a/arch/openrisc/lib/Makefile
> +++ b/arch/openrisc/lib/Makefile
> @@ -4,3 +4,4 @@ obj-y                 += cpuinfo.o
>  obj-y                 += muldi3.o
>  obj-y                 += lshrdi3.o
>  obj-y                 += ashldi3.o
> +obj-y                 += ashrdi3.o
> diff --git a/arch/openrisc/lib/ashrdi3.S b/arch/openrisc/lib/ashrdi3.S
> new file mode 100644
> index 0000000..c656d9f
> --- /dev/null
> +++ b/arch/openrisc/lib/ashrdi3.S
> @@ -0,0 +1,59 @@
> +/*
> + * (C) Copyright 2012 - Franck JULLIEN <elec4fun@gmail.com>
> + *
> + * Extracted from gcc generated assembly.
> + *
> + * Extended precision shifts.
> + *
> + * R3/R4 (MSW, LSW) has 64 bit value
> + * R5    has shift count
> + * result in R11/R12
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +.globl __ashrdi3
> +
> +__ashrdi3:
> +	l.sfeqi r5,0x0			/* if count = 0, go out                   */
> +	l.bf out
> +
> +	l.addi r6,r0,0x20		/* r6 = 32                                */
> +	l.sub r6,r6,r5			/* r6 = 32 - count                        */
> +	l.sfgtsi r6,0x0			/* if count >= 32                         */
> +	l.bnf more_than_32		/* branch to more_than_32                 */
> +	l.nop 0x0
> +
> +
> + less_than_32:
> +	l.sll r6,r3,r6			/* r6 gets the bits moved from MSW to LSW */
> +	l.srl r4,r4,r5			/* shift LSW                              */
> +	l.sra r5,r3,r5			/* shift MSW to r5                        */
> +	l.or r4,r6,r4			/* LSW gets bits shifted from MSW         */
> +	l.ori r3,r5,0x0			/* r3 = MSW                               */
> +
> + out:
> +	l.ori r11,r3,0x0
> +	l.jr r9
> +	l.ori r12,r4,0x0
> +
> + more_than_32:
> +	l.srai r5,r3,0x1f		/* r5 = MSW sign extended                 */
> +	l.sub r4,r0,r6			/* r4 = -r6, the number of bits above 32  */
> +	l.sra r4,r3,r4			/* LSW gets bits shifted from MSB         */
> +	l.j out				/* go out                                 */
> +	l.ori r3,r5,0x0			/* r3 = MSW                               */
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-09-14  6:41 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-09-12 22:28 [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Franck Jullien
2012-09-12 22:28 ` [PATCH 2/3] Add OpenRISC Image type Franck Jullien
2012-09-12 22:28 ` [PATCH 3/3] [MCI_SPI] Fix endianness error on be target Franck Jullien
2012-09-14  6:40 ` [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc Sascha Hauer

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