From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Limit the ioremap of the PCI bar to the registers
Date: Fri, 14 Sep 2012 23:27:46 +0200 [thread overview]
Message-ID: <20120914212746.GH5799@phenom.ffwll.local> (raw)
In-Reply-To: <20120914115030.5a11a2ee@bwidawsk.net>
On Fri, Sep 14, 2012 at 11:50:30AM -0700, Ben Widawsky wrote:
> On Fri, 14 Sep 2012 11:57:46 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> > In the future we may like to experiment with using a WC map of the GTT
> > portion. However, that will conflict with i915.ko mapping the entire bar
> > as UC in order to access the GPU registers. Instead we can shrink the
> > register ioremap to only map the register block.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Since I really don't want to pull out docs for anything less than
> gen6...
> Tested-by (IVB): Ben Widawsky <ben@bwidawsk.net>
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
Both patches merged, with the commit message frobbed.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2012-09-14 21:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-14 10:57 [PATCH 1/2] drm/i915: Limit the ioremap of the PCI bar to the registers Chris Wilson
2012-09-14 10:57 ` [PATCH 2/2] agp/intel: Use a write-combining map for updating PTEs Chris Wilson
2012-09-14 11:08 ` Chris Wilson
2012-09-14 18:50 ` [PATCH 1/2] drm/i915: Limit the ioremap of the PCI bar to the registers Ben Widawsky
2012-09-14 21:27 ` Daniel Vetter [this message]
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