From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] agp/intel: Use a write-combining map for updating PTEs
Date: Fri, 14 Sep 2012 12:08:06 +0100 [thread overview]
Message-ID: <275ffc$6jn85r@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1347620267-11275-2-git-send-email-chris@chris-wilson.co.uk>
On Fri, 14 Sep 2012 11:57:47 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> v2: Limit the WC mapping to older generations as we should the TLB
> invalidation on SandyBridge+ unreliable.
/me fires his editor and proof-reader
v2: Limit the WC mapping to older generations as we have observed that
the TLB invalidation on SandyBridge+ is unreliable with WC updates.
See i-g-t/tests/gem_gtt_cpu_tlb
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-09-14 11:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-14 10:57 [PATCH 1/2] drm/i915: Limit the ioremap of the PCI bar to the registers Chris Wilson
2012-09-14 10:57 ` [PATCH 2/2] agp/intel: Use a write-combining map for updating PTEs Chris Wilson
2012-09-14 11:08 ` Chris Wilson [this message]
2012-09-14 18:50 ` [PATCH 1/2] drm/i915: Limit the ioremap of the PCI bar to the registers Ben Widawsky
2012-09-14 21:27 ` Daniel Vetter
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