[PATCH v2 0/9] Enable all display interfaces in Valleyview

[PATCH v2 0/9] Enable all display interfaces in Valleyview

[Vijay Purushothaman]

This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display configurations.

v2: Addressed review comments from Daniel and Jani Nikula.

Gajanan Bhat (1):
  drm/i915: Add eDP support for Valleyview

Vijay Purushothaman (8):
  drm/i915: Set aux clk to 100MHz for Valleyview
  drm/i915: Fix SDVO IER and status bits for Valleyview
  drm/i915: Add Valleyview lane control definitions
  drm/i915: Program correct m n tu register for Valleyview
  drm/i915: Disable CRT hotplug detection for valleyview
  drm/i915: Enable DisplayPort in Valleyview
  drm/i915: panel power sequencing for VLV eDP
  drm/i915: Fixup HDMI output on Valleyview

 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |   15 +++-
 drivers/gpu/drm/i915/intel_crt.c     |    7 ++
 drivers/gpu/drm/i915/intel_display.c |  113 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dp.c      |  152 ++++++++++++++++++++++++----------
 5 files changed, 211 insertions(+), 82 deletions(-)

-- 
1.7.9.5

[PATCH v2 1/9] drm/i915: Set aux clk to 100MHz for Valleyview

[Vijay Purushothaman]

Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a69d9a2..de8092a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t clkcfg;
 
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
 	clkcfg = I915_READ(CLKCFG);
 	switch (clkcfg & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_400:
@@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if (IS_VALLEYVIEW(dev))
+			aux_clock_divider = 100;
+		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
-- 
1.7.9.5

[PATCH v2 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview

[Vijay Purushothaman]

Fixed SDVOB and SDVOC bit definitions for Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d915126..1a974d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 #endif
 
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-#if 0 /* FIXME: check register definitions; some have moved */
 	/* Note HDMI and DP share bits */
 	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
@@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMID_HOTPLUG_INT_EN;
-	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
-	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
 		hotplug_en |= CRT_HOTPLUG_INT_EN;
 		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
 	}
-#endif
 
 	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 
-- 
1.7.9.5

[PATCH v2 3/9] drm/i915: Add Valleyview lane control definitions

[Vijay Purushothaman]

Added DPIO data lane register definitions for Valleyview

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828e90..3f75ee6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -369,6 +369,7 @@
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_PLL_REFCLK_SEL_MASK	3
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
 #define _DPIO_REFSFR_B			0x8034
@@ -384,6 +385,13 @@
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
+#define _DPIO_DATA_LANE0		0x0220
+#define _DPIO_DATA_LANE1		0x0420
+#define _DPIO_DATA_LANE2		0x2620
+#define _DPIO_DATA_LANE3		0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+
 /*
  * Fence registers
  */
-- 
1.7.9.5

[PATCH v2 4/9] drm/i915: Program correct m n tu register for Valleyview

[Vijay Purushothaman]

m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 +++---
 drivers/gpu/drm/i915/intel_dp.c      |    5 +++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
 };
 
 static const intel_limit_t intel_limits_vlv_dp = {
-	.dot = { .min = 162000, .max = 270000 },
-	.vco = { .min = 5994000, .max = 4000000 },
+	.dot = { .min = 25000, .max = 270000 },
+	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
-	.m = { .min = 60, .max = 300 }, /* guess */
+	.m = { .min = 22, .max = 450 },
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+	} else if (IS_VALLEYVIEW(dev)) {
+		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 	} else {
 		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-- 
1.7.9.5

[PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview

[Vijay Purushothaman]

Temporary work around to avoid spurious crt hotplug interrupts.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c42b980..5f30364 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 	bool ret;
 	u32 save_adpa;
 
+	/*
+	 * Disable crt detect hotplug for VLV X0. Spurious hot plug
+	 * detect calls crashses the X0 system
+	 */
+	if (IS_VALLEYVIEW(dev))
+		return false;
+
 	save_adpa = adpa = I915_READ(ADPA);
 	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
-- 
1.7.9.5

[PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview

[Vijay Purushothaman]

In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.

Cleaned up DPLL calculations for Valleyview to support multi display
configurations.

v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    8 +--
 drivers/gpu/drm/i915/intel_display.c |   90 ++++++++++++++++++++++++----------
 2 files changed, 66 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..0fe4aad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
-#define _DPIO_DATA_LANE0		0x0220
-#define _DPIO_DATA_LANE1		0x0420
-#define _DPIO_DATA_LANE2		0x2620
-#define _DPIO_DATA_LANE3		0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1		0x8220
+#define DPIO_DATA_CHANNEL2		0x8420
 
 /*
  * Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..ed749c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 			   struct drm_display_mode *mode,
 			   struct drm_display_mode *adjusted_mode,
 			   intel_clock_t *clock, intel_clock_t *reduced_clock,
-			   int refclk, int num_connectors)
+			   int num_connectors)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 dpll, mdiv, pdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	bool is_hdmi;
+	bool is_sdvo;
+	u32 temp;
+
+	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
 
-	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+	dpll = DPLL_VGA_MODE_DIS;
+	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
 
 	bestn = clock->n;
 	bestm1 = clock->m1;
@@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	bestp1 = clock->p1;
 	bestp2 = clock->p2;
 
-	/* Enable DPIO clock input */
-	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
-		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
-
+	/*
+	 * In Valleyview PLL and program lane counter registers are exposed
+	 * through DPIO interface
+	 */
 	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
@@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 
 	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
 
-	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
 		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
-		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
+		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
 	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
 
-	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
 
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll);
@@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("DPLL %d failed to lock\n", pipe);
 
-	if (is_hdmi) {
-		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
 
+	temp = 0;
+	if (is_sdvo) {
+		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
 		if (temp > 1)
 			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		else
 			temp = 0;
-
-		I915_WRITE(DPLL_MD(pipe), temp);
-		POSTING_READ(DPLL_MD(pipe));
 	}
+	I915_WRITE(DPLL_MD(pipe), temp);
+	POSTING_READ(DPLL_MD(pipe));
 
-	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+	/* Now program lane control registers */
+	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
+			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+	{
+		temp = 0x1000C4;
+		if(pipe == 1)
+			temp |= (1 << 21);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
+	}
+	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
+	{
+		temp = 0x1000C4;
+		if(pipe == 1)
+			temp |= (1 << 21);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
+	}
 }
 
+
 static void i9xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode,
@@ -4092,9 +4127,10 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	u32 dpll;
 	bool is_sdvo;
 
+	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
+
 	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
 		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
-
 	dpll = DPLL_VGA_MODE_DIS;
 
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
@@ -4192,7 +4228,7 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 
 static void i8xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *adjusted_mode,
-			    intel_clock_t *clock,
+			    intel_clock_t *clock, intel_clock_t *reduced_clock,
 			    int num_connectors)
 {
 	struct drm_device *dev = crtc->dev;
@@ -4201,6 +4237,8 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 dpll;
 
+	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
+
 	dpll = DPLL_VGA_MODE_DIS;
 
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -4327,14 +4365,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	if (is_sdvo && is_tv)
 		i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
 
-	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
-				 &reduced_clock : NULL);
-
 	if (IS_GEN2(dev))
-		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
+		i8xx_update_pll(crtc, adjusted_mode, &clock,
+				has_reduced_clock ? &reduced_clock : NULL,
+				num_connectors);
 	else if (IS_VALLEYVIEW(dev))
-		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
-			       refclk, num_connectors);
+		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
+				has_reduced_clock ? &reduced_clock : NULL,
+				num_connectors);
 	else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
-- 
1.7.9.5

[PATCH v2 7/9] drm/i915: Add eDP support for Valleyview

[Vijay Purushothaman]

From: Gajanan Bhat <gajanan.bhat@intel.com>

Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.

v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
v4: removed unconditional enabling of 6bpc dithering based on comments
from Daniel & Jani Nikula. Also changed the display enabling order to
force eDP detection first.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   15 ++++++++++++---
 drivers/gpu/drm/i915/intel_dp.c      |   17 ++++++++++++-----
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ed749c4..0362c80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4413,6 +4413,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		}
 	}
 
+	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
+			pipeconf |= PIPECONF_BPP_6 |
+					PIPECONF_ENABLE |
+					I965_PIPECONF_ACTIVE;
+		}
+	}
+
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
@@ -7623,6 +7631,10 @@ static void intel_setup_outputs(struct drm_device *dev)
 	} else if (IS_VALLEYVIEW(dev)) {
 		int found;
 
+		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
+		if (I915_READ(DP_C) & DP_DETECTED)
+			intel_dp_init(dev, DP_C, PORT_C);
+
 		if (I915_READ(SDVOB) & PORT_DETECTED) {
 			/* SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev, SDVOB, true);
@@ -7635,9 +7647,6 @@ static void intel_setup_outputs(struct drm_device *dev)
 		if (I915_READ(SDVOC) & PORT_DETECTED)
 			intel_hdmi_init(dev, SDVOC, PORT_C);
 
-		/* Shares lanes with HDMI on SDVOC */
-		if (I915_READ(DP_C) & DP_DETECTED)
-			intel_dp_init(dev, DP_C, PORT_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..867c568 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		uint32_t    signal_levels;
 
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,14 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		if (intel_dpd_is_edp(dev))
 			intel_dp->is_pch_edp = true;
 
-	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
+	/*
+	 * FIXME : We need to initialize built-in panels before external panels.
+	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
+	 */
+	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
+		type = DRM_MODE_CONNECTOR_eDP;
+		intel_encoder->type = INTEL_OUTPUT_EDP;
+	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 	} else {
-- 
1.7.9.5

[PATCH v2 8/9] drm/i915: panel power sequencing for VLV eDP

[Vijay Purushothaman]

PPS register offsets have changed in Valleyview.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    9 +++
 drivers/gpu/drm/i915/intel_dp.c |  122 +++++++++++++++++++++++++++------------
 2 files changed, 93 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fe4aad..0e6258a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3977,6 +3977,15 @@
 #define PIPEB_PP_ON_DELAYS      0x61308
 #define PIPEB_PP_OFF_DELAYS     0x6130c
 #define PIPEB_PP_DIVISOR        0x61310
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
 
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 867c568..c58535b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg;
 
-	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_ctrl_reg;
 
-	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 }
 
 static void
@@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
 	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 		WARN(1, "eDP powered off while attempting aux channel communication.\n");
 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS),
-			      I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 
 	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
-		      mask, value,
-		      I915_READ(PCH_PP_STATUS),
-		      I915_READ(PCH_PP_CONTROL));
+			mask, value,
+			I915_READ(pp_stat_reg),
+			I915_READ(pp_ctrl_reg));
 
-	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
-			  I915_READ(PCH_PP_STATUS),
-			  I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  * is locked
  */
 
-static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 {
-	u32	control = I915_READ(PCH_PP_CONTROL);
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 control;
+	u32 pp_ctrl_reg;
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	control = I915_READ(pp_ctrl_reg);
 
 	control &= ~PANEL_UNLOCK_MASK;
 	control |= PANEL_UNLOCK_REGS;
@@ -994,6 +1013,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1012,13 +1032,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	if (!ironlake_edp_have_panel_power(intel_dp))
 		ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_FORCE_VDD;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
-	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
+	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 	/*
 	 * If the panel wasn't on, delay before accessing aux channel
 	 */
@@ -1033,17 +1056,21 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
-		pp = ironlake_get_pp_control(dev_priv);
+		pp = ironlake_get_pp_control(intel_dp);
 		pp &= ~EDP_FORCE_VDD;
-		I915_WRITE(PCH_PP_CONTROL, pp);
-		POSTING_READ(PCH_PP_CONTROL);
 
-		/* Make sure sequencer is idle before allowing subsequent activity */
-		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 
+		I915_WRITE(pp_ctrl_reg, pp);
+		POSTING_READ(pp_ctrl_reg);
+
+		/* Make sure sequencer is idle before allowing subsequent activity */
+		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 		msleep(intel_dp->panel_power_down_delay);
 	}
 }
@@ -1087,6 +1114,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1100,7 +1128,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 
 	ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	if (IS_GEN5(dev)) {
 		/* ILK workaround: disable reset around power sequence */
 		pp &= ~PANEL_POWER_RESET;
@@ -1112,8 +1140,10 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	if (!IS_GEN5(dev))
 		pp |= PANEL_POWER_RESET;
 
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	ironlake_wait_panel_on(intel_dp);
 
@@ -1129,6 +1159,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1137,12 +1168,15 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 
 	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	/* We need to switch off panel power _and_ force vdd, for otherwise some
 	 * panels get very unhappy and cease to work. */
 	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	intel_dp->want_panel_vdd = false;
 
@@ -1154,6 +1188,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1166,10 +1201,13 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	 * allowing it to appear.
 	 */
 	msleep(intel_dp->backlight_on_delay);
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 }
 
 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
@@ -1177,15 +1215,17 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
 
 	DRM_DEBUG_KMS("\n");
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp &= ~EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 	msleep(intel_dp->backlight_off_delay);
 }
 
@@ -2547,9 +2587,15 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		u32 pp_on, pp_off, pp_div;
 		struct edid *edid;
 
-		pp_on = I915_READ(PCH_PP_ON_DELAYS);
-		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
-		pp_div = I915_READ(PCH_PP_DIVISOR);
+		if (IS_VALLEYVIEW(dev)) {
+			pp_on = I915_READ(PIPEA_PP_ON_DELAYS);
+			pp_off = I915_READ(PIPEA_PP_OFF_DELAYS);
+			pp_div = I915_READ(PIPEA_PP_DIVISOR);
+		} else {
+			pp_on = I915_READ(PCH_PP_ON_DELAYS);
+			pp_off = I915_READ(PCH_PP_OFF_DELAYS);
+			pp_div = I915_READ(PCH_PP_DIVISOR);
+		}
 
 		if (!pp_on || !pp_off || !pp_div) {
 			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
-- 
1.7.9.5

[PATCH v2 9/9] drm/i915: Fixup HDMI output on Valleyview

[Vijay Purushothaman]

Fixed correct min, max vco limits and dip ctl reg

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 +-
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e6258a..71aa0a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3683,7 +3683,7 @@
 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
-#define VLV_VIDEO_DIP_CTL_A		0x60220
+#define VLV_VIDEO_DIP_CTL_A		0x60200
 #define VLV_VIDEO_DIP_DATA_A		0x60208
 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0362c80..64c94ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
 
 static const intel_limit_t intel_limits_vlv_hdmi = {
 	.dot = { .min = 20000, .max = 165000 },
-	.vco = { .min = 5994000, .max = 4000000 },
+	.vco = { .min = 4000000, .max = 5994000},
 	.n = { .min = 1, .max = 7 },
 	.m = { .min = 60, .max = 300 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
-- 
1.7.9.5

Re: [PATCH v2 1/9] drm/i915: Set aux clk to 100MHz for Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:01 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
> This enables the aux transactions in Valleyview.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a69d9a2..de8092a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t clkcfg;
>  
> +	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> +	if (IS_VALLEYVIEW(dev))
> +		return 200;
> +
>  	clkcfg = I915_READ(CLKCFG);
>  	switch (clkcfg & CLKCFG_FSB_MASK) {
>  	case CLKCFG_FSB_400:
> @@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  	 * clock divider.
>  	 */
>  	if (is_cpu_edp(intel_dp)) {
> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> +		if (IS_VALLEYVIEW(dev))
> +			aux_clock_divider = 100;
> +		else if (IS_GEN6(dev) || IS_GEN7(dev))
>  			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
>  		else
>  			aux_clock_divider = 225; /* eDP input clock at 450Mhz */

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Hopefully I'll get a chance to test later today.  I'm tracking down a
regression in the gmbus based edid probing in the -next based tree I'm
using...

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:02 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Fixed SDVOB and SDVOC bit definitions for Valleyview.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d915126..1a974d9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  #endif
>  
>  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> -#if 0 /* FIXME: check register definitions; some have moved */
>  	/* Note HDMI and DP share bits */
>  	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
>  		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
> @@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
>  	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
>  		hotplug_en |= HDMID_HOTPLUG_INT_EN;
> -	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
> +	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
>  		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
> -	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
> +	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
>  		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
>  	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
>  		hotplug_en |= CRT_HOTPLUG_INT_EN;
>  		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
>  	}
> -#endif
>  
>  	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
>  

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 3/9] drm/i915: Add Valleyview lane control definitions

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:03 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Added DPIO data lane register definitions for Valleyview
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a828e90..3f75ee6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -369,6 +369,7 @@
>  #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
>  #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
>  #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> +#define   DPIO_PLL_REFCLK_SEL_MASK	3
>  #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
>  #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
>  #define _DPIO_REFSFR_B			0x8034
> @@ -384,6 +385,13 @@
>  
>  #define DPIO_FASTCLK_DISABLE		0x8100
>  
> +#define _DPIO_DATA_LANE0		0x0220
> +#define _DPIO_DATA_LANE1		0x0420
> +#define _DPIO_DATA_LANE2		0x2620
> +#define _DPIO_DATA_LANE3		0x2820
> +#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> +#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> +
>  /*
>   * Fence registers
>   */

The lane regs don't match what I have in one of my docs (it has 120,
220, 2320, 2420), but I think it's for CDV, so I'll take your word
for it.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 4/9] drm/i915: Program correct m n tu register for Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:04 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> m n tu register offset has changed in Valleyview. Also fixed DP limit
> frequencies.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    6 +++---
>  drivers/gpu/drm/i915/intel_dp.c      |    5 +++++
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 947c97d..68828e7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
>  };
>  
>  static const intel_limit_t intel_limits_vlv_dp = {
> -	.dot = { .min = 162000, .max = 270000 },
> -	.vco = { .min = 5994000, .max = 4000000 },
> +	.dot = { .min = 25000, .max = 270000 },
> +	.vco = { .min = 4000000, .max = 6000000 },
>  	.n = { .min = 1, .max = 7 },
> -	.m = { .min = 60, .max = 300 }, /* guess */
> +	.m = { .min = 22, .max = 450 },
>  	.m1 = { .min = 2, .max = 3 },
>  	.m2 = { .min = 11, .max = 156 },
>  	.p = { .min = 10, .max = 30 },
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index de8092a..c111c3f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
>  		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
>  		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
>  		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> +		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> +		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> +		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
>  	} else {
>  		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
>  			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:05 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Temporary work around to avoid spurious crt hotplug interrupts.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c42b980..5f30364 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>  	bool ret;
>  	u32 save_adpa;
>  
> +	/*
> +	 * Disable crt detect hotplug for VLV X0. Spurious hot plug
> +	 * detect calls crashses the X0 system
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		return false;
> +
>  	save_adpa = adpa = I915_READ(ADPA);
>  	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>  

Not sure about this one; your platform seems to be less stable than
mine when it comes to both VGA port handling and legacy VGA I/O...  But
I have no problem with it either, I just know it works ok on at least
some of the SDVs, probably depending on board rework and firmware
status.

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:06 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> In valleyview voltageswing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric.
> 
> Cleaned up DPLL calculations for Valleyview to support multi display
> configurations.
> 
> v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
> patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
> i9xx_update_pll.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    8 +--
>  drivers/gpu/drm/i915/intel_display.c |   90 ++++++++++++++++++++++++----------
>  2 files changed, 66 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f75ee6..0fe4aad 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -385,12 +385,8 @@
>  
>  #define DPIO_FASTCLK_DISABLE		0x8100
>  
> -#define _DPIO_DATA_LANE0		0x0220
> -#define _DPIO_DATA_LANE1		0x0420
> -#define _DPIO_DATA_LANE2		0x2620
> -#define _DPIO_DATA_LANE3		0x2820
> -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> +#define DPIO_DATA_CHANNEL1		0x8220
> +#define DPIO_DATA_CHANNEL2		0x8420
>  
>  /*
>   * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 68828e7..ed749c4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  			   struct drm_display_mode *mode,
>  			   struct drm_display_mode *adjusted_mode,
>  			   intel_clock_t *clock, intel_clock_t *reduced_clock,
> -			   int refclk, int num_connectors)
> +			   int num_connectors)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll, mdiv, pdiv;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> -	bool is_hdmi;
> +	bool is_sdvo;
> +	u32 temp;
> +
> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>  
> -	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +	dpll = DPLL_VGA_MODE_DIS;
> +	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> +	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> +	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +	POSTING_READ(DPLL(pipe));
>  
>  	bestn = clock->n;
>  	bestm1 = clock->m1;
> @@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	bestp1 = clock->p1;
>  	bestp2 = clock->p2;
>  
> -	/* Enable DPIO clock input */
> -	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> -		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
> -	I915_WRITE(DPLL(pipe), dpll);
> -	POSTING_READ(DPLL(pipe));
> -
> +	/*
> +	 * In Valleyview PLL and program lane counter registers are exposed
> +	 * through DPIO interface
> +	 */
>  	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
>  	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>  	mdiv |= ((bestn << DPIO_N_SHIFT));
> @@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  
>  	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
>  
> -	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> +	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
>  		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> -		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> +		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
> +		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
>  	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
>  
> -	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
>  
>  	dpll |= DPLL_VCO_ENABLE;
>  	I915_WRITE(DPLL(pipe), dpll);
> @@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>  		DRM_ERROR("DPLL %d failed to lock\n", pipe);
>  
> -	if (is_hdmi) {
> -		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
>  
> +	temp = 0;
> +	if (is_sdvo) {
> +		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>  		if (temp > 1)
>  			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  		else
>  			temp = 0;
> -
> -		I915_WRITE(DPLL_MD(pipe), temp);
> -		POSTING_READ(DPLL_MD(pipe));
>  	}
> +	I915_WRITE(DPLL_MD(pipe), temp);
> +	POSTING_READ(DPLL_MD(pipe));
>  
> -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
> +	/* Now program lane control registers */
> +	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
> +			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> +	{
> +		temp = 0x1000C4;
> +		if(pipe == 1)
> +			temp |= (1 << 21);
> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
> +	}
> +	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
> +	{
> +		temp = 0x1000C4;
> +		if(pipe == 1)
> +			temp |= (1 << 21);
> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
> +	}
>  }
>  
> +
>  static void i9xx_update_pll(struct drm_crtc *crtc,
>  			    struct drm_display_mode *mode,
>  			    struct drm_display_mode *adjusted_mode,
> @@ -4092,9 +4127,10 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	u32 dpll;
>  	bool is_sdvo;
>  
> +	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
> +
>  	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>  		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> -
>  	dpll = DPLL_VGA_MODE_DIS;
>  
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> @@ -4192,7 +4228,7 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  
>  static void i8xx_update_pll(struct drm_crtc *crtc,
>  			    struct drm_display_mode *adjusted_mode,
> -			    intel_clock_t *clock,
> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
>  			    int num_connectors)
>  {
>  	struct drm_device *dev = crtc->dev;
> @@ -4201,6 +4237,8 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll;
>  
> +	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
> +
>  	dpll = DPLL_VGA_MODE_DIS;
>  
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> @@ -4327,14 +4365,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	if (is_sdvo && is_tv)
>  		i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
>  
> -	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
> -				 &reduced_clock : NULL);
> -
>  	if (IS_GEN2(dev))
> -		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> +		i8xx_update_pll(crtc, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  	else if (IS_VALLEYVIEW(dev))
> -		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
> -			       refclk, num_connectors);
> +		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  	else
>  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>  				has_reduced_clock ? &reduced_clock : NULL,

Looks good.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 7/9] drm/i915: Add eDP support for Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:07 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> From: Gajanan Bhat <gajanan.bhat@intel.com>
> 
> Eventhough Valleyview display block is derived from Cantiga, VLV
> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> 
> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> v3: fix DPIO value calculation to use same values for all display
> interfaces
> v4: removed unconditional enabling of 6bpc dithering based on comments
> from Daniel & Jani Nikula. Also changed the display enabling order to
> force eDP detection first.
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   15 ++++++++++++---
>  drivers/gpu/drm/i915/intel_dp.c      |   17 ++++++++++++-----
>  2 files changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ed749c4..0362c80 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4413,6 +4413,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		}
>  	}
>  
> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> +		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> +			pipeconf |= PIPECONF_BPP_6 |
> +					PIPECONF_ENABLE |
> +					I965_PIPECONF_ACTIVE;
> +		}
> +	}
> +
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> @@ -7623,6 +7631,10 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		int found;
>  
> +		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
> +		if (I915_READ(DP_C) & DP_DETECTED)
> +			intel_dp_init(dev, DP_C, PORT_C);
> +
>  		if (I915_READ(SDVOB) & PORT_DETECTED) {
>  			/* SDVOB multiplex with HDMIB */
>  			found = intel_sdvo_init(dev, SDVOB, true);
> @@ -7635,9 +7647,6 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		if (I915_READ(SDVOC) & PORT_DETECTED)
>  			intel_hdmi_init(dev, SDVOC, PORT_C);
>  
> -		/* Shares lanes with HDMI on SDVOC */
> -		if (I915_READ(DP_C) & DP_DETECTED)
> -			intel_dp_init(dev, DP_C, PORT_C);
>  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
>  		bool found = false;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c111c3f..867c568 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>  
>  	/* Split out the IBX/CPU vs CPT settings */
>  
> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  
> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_400:
>  			return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  		uint32_t    signal_levels;
>  
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  			break;
>  		}
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -2471,7 +2471,14 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  		if (intel_dpd_is_edp(dev))
>  			intel_dp->is_pch_edp = true;
>  
> -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> +	/*
> +	 * FIXME : We need to initialize built-in panels before external panels.
> +	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
> +	 */
> +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> +		type = DRM_MODE_CONNECTOR_eDP;
> +		intel_encoder->type = INTEL_OUTPUT_EDP;
> +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>  		type = DRM_MODE_CONNECTOR_eDP;
>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>  	} else {

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 8/9] drm/i915: panel power sequencing for VLV eDP

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:08 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> PPS register offsets have changed in Valleyview.
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    9 +++
>  drivers/gpu/drm/i915/intel_dp.c |  122 +++++++++++++++++++++++++++------------
>  2 files changed, 93 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0fe4aad..0e6258a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3977,6 +3977,15 @@
>  #define PIPEB_PP_ON_DELAYS      0x61308
>  #define PIPEB_PP_OFF_DELAYS     0x6130c
>  #define PIPEB_PP_DIVISOR        0x61310
> +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe) \
> +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> +
>  
>  #define PCH_PP_STATUS		0xc7200
>  #define PCH_PP_CONTROL		0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 867c568..c58535b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg;
>  
> -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
>  }
>  
>  static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_ctrl_reg;
>  
> -	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
>  }
>  
>  static void
> @@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> +
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
>  	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
>  		WARN(1, "eDP powered off while attempting aux channel communication.\n");
>  		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
> -			      I915_READ(PCH_PP_STATUS),
> -			      I915_READ(PCH_PP_CONTROL));
> +				I915_READ(pp_stat_reg),
> +				I915_READ(pp_ctrl_reg));
>  	}
>  }
>  
> @@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg, pp_ctrl_reg;
> +
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>  
>  	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
> -		      mask, value,
> -		      I915_READ(PCH_PP_STATUS),
> -		      I915_READ(PCH_PP_CONTROL));
> +			mask, value,
> +			I915_READ(pp_stat_reg),
> +			I915_READ(pp_ctrl_reg));
>  
> -	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
> +	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
>  		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
> -			  I915_READ(PCH_PP_STATUS),
> -			  I915_READ(PCH_PP_CONTROL));
> +				I915_READ(pp_stat_reg),
> +				I915_READ(pp_ctrl_reg));
>  	}
>  }
>  
> @@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
>   * is locked
>   */
>  
> -static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
> +static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
>  {
> -	u32	control = I915_READ(PCH_PP_CONTROL);
> +	struct drm_device *dev = intel_dp->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 control;
> +	u32 pp_ctrl_reg;
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	control = I915_READ(pp_ctrl_reg);
>  
>  	control &= ~PANEL_UNLOCK_MASK;
>  	control |= PANEL_UNLOCK_REGS;
> @@ -994,6 +1013,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1012,13 +1032,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
>  	if (!ironlake_edp_have_panel_power(intel_dp))
>  		ironlake_wait_panel_power_cycle(intel_dp);
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp |= EDP_FORCE_VDD;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> -	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> -		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
>  
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
> +	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> +			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  	/*
>  	 * If the panel wasn't on, delay before accessing aux channel
>  	 */
> @@ -1033,17 +1056,21 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
> -		pp = ironlake_get_pp_control(dev_priv);
> +		pp = ironlake_get_pp_control(intel_dp);
>  		pp &= ~EDP_FORCE_VDD;
> -		I915_WRITE(PCH_PP_CONTROL, pp);
> -		POSTING_READ(PCH_PP_CONTROL);
>  
> -		/* Make sure sequencer is idle before allowing subsequent activity */
> -		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> -			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
> +		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>  
> +		I915_WRITE(pp_ctrl_reg, pp);
> +		POSTING_READ(pp_ctrl_reg);
> +
> +		/* Make sure sequencer is idle before allowing subsequent activity */
> +		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> +		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  		msleep(intel_dp->panel_power_down_delay);
>  	}
>  }
> @@ -1087,6 +1114,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1100,7 +1128,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  
>  	ironlake_wait_panel_power_cycle(intel_dp);
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	if (IS_GEN5(dev)) {
>  		/* ILK workaround: disable reset around power sequence */
>  		pp &= ~PANEL_POWER_RESET;
> @@ -1112,8 +1140,10 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  	if (!IS_GEN5(dev))
>  		pp |= PANEL_POWER_RESET;
>  
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  
>  	ironlake_wait_panel_on(intel_dp);
>  
> @@ -1129,6 +1159,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1137,12 +1168,15 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>  
>  	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	/* We need to switch off panel power _and_ force vdd, for otherwise some
>  	 * panels get very unhappy and cease to work. */
>  	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  
>  	intel_dp->want_panel_vdd = false;
>  
> @@ -1154,6 +1188,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1166,10 +1201,13 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>  	 * allowing it to appear.
>  	 */
>  	msleep(intel_dp->backlight_on_delay);
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp |= EDP_BLC_ENABLE;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  }
>  
>  static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> @@ -1177,15 +1215,17 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
>  
>  	DRM_DEBUG_KMS("\n");
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp &= ~EDP_BLC_ENABLE;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  	msleep(intel_dp->backlight_off_delay);
>  }
>  
> @@ -2547,9 +2587,15 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  		u32 pp_on, pp_off, pp_div;
>  		struct edid *edid;
>  
> -		pp_on = I915_READ(PCH_PP_ON_DELAYS);
> -		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> -		pp_div = I915_READ(PCH_PP_DIVISOR);
> +		if (IS_VALLEYVIEW(dev)) {
> +			pp_on = I915_READ(PIPEA_PP_ON_DELAYS);
> +			pp_off = I915_READ(PIPEA_PP_OFF_DELAYS);
> +			pp_div = I915_READ(PIPEA_PP_DIVISOR);
> +		} else {
> +			pp_on = I915_READ(PCH_PP_ON_DELAYS);
> +			pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> +			pp_div = I915_READ(PCH_PP_DIVISOR);
> +		}
>  
>  		if (!pp_on || !pp_off || !pp_div) {
>  			DRM_INFO("bad panel power sequencing delays, disabling panel\n");

I think Daniel's right that it would be good to abstract this a bit.
Pretty sure people are building machines with multiple embedded panels
and using some i2c interface for doing the secondary sequence.  A good
abstraction would help with that too.

Jesse

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 9/9] drm/i915: Fixup HDMI output on Valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:09 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Fixed correct min, max vco limits and dip ctl reg
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    2 +-
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0e6258a..71aa0a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3683,7 +3683,7 @@
>  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
> -#define VLV_VIDEO_DIP_CTL_A		0x60220
> +#define VLV_VIDEO_DIP_CTL_A		0x60200
>  #define VLV_VIDEO_DIP_DATA_A		0x60208
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0362c80..64c94ca 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
>  
>  static const intel_limit_t intel_limits_vlv_hdmi = {
>  	.dot = { .min = 20000, .max = 165000 },
> -	.vco = { .min = 5994000, .max = 4000000 },
> +	.vco = { .min = 4000000, .max = 5994000},
>  	.n = { .min = 1, .max = 7 },
>  	.m = { .min = 60, .max = 300 }, /* guess */
>  	.m1 = { .min = 2, .max = 3 },

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview

[Jesse Barnes]

On Thu, 27 Sep 2012 19:13:05 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Temporary work around to avoid spurious crt hotplug interrupts.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c42b980..5f30364 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>  	bool ret;
>  	u32 save_adpa;
>  
> +	/*
> +	 * Disable crt detect hotplug for VLV X0. Spurious hot plug
> +	 * detect calls crashses the X0 system
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		return false;
> +
>  	save_adpa = adpa = I915_READ(ADPA);
>  	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>  

Oh and since this is a vlv specific function, the IS_VLV check is
unnecessary.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH v2 8/9] drm/i915: panel power sequencing for VLV eDP

[Daniel Vetter]

On Thu, Sep 27, 2012 at 08:26:15AM -0700, Jesse Barnes wrote:
> On Thu, 27 Sep 2012 19:13:08 +0530
> Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:
> 
> > PPS register offsets have changed in Valleyview.
> > 
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    9 +++
> >  drivers/gpu/drm/i915/intel_dp.c |  122 +++++++++++++++++++++++++++------------
> >  2 files changed, 93 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0fe4aad..0e6258a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3977,6 +3977,15 @@
> >  #define PIPEB_PP_ON_DELAYS      0x61308
> >  #define PIPEB_PP_OFF_DELAYS     0x6130c
> >  #define PIPEB_PP_DIVISOR        0x61310
> > +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> > +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> > +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> > +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> > +#define VLV_PIPE_PP_DIVISOR(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> > +
> >  
> >  #define PCH_PP_STATUS		0xc7200
> >  #define PCH_PP_CONTROL		0xc7204
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 867c568..c58535b 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_stat_reg;
> >  
> > -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> > +	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
> >  }
> >  
> >  static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_ctrl_reg;
> >  
> > -	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
> >  }
> >  
> >  static void
> > @@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_stat_reg, pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> > +
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +
> >  	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
> >  		WARN(1, "eDP powered off while attempting aux channel communication.\n");
> >  		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
> > -			      I915_READ(PCH_PP_STATUS),
> > -			      I915_READ(PCH_PP_CONTROL));
> > +				I915_READ(pp_stat_reg),
> > +				I915_READ(pp_ctrl_reg));
> >  	}
> >  }
> >  
> > @@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_stat_reg, pp_ctrl_reg;
> > +
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> >  
> >  	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
> > -		      mask, value,
> > -		      I915_READ(PCH_PP_STATUS),
> > -		      I915_READ(PCH_PP_CONTROL));
> > +			mask, value,
> > +			I915_READ(pp_stat_reg),
> > +			I915_READ(pp_ctrl_reg));
> >  
> > -	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
> > +	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
> >  		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
> > -			  I915_READ(PCH_PP_STATUS),
> > -			  I915_READ(PCH_PP_CONTROL));
> > +				I915_READ(pp_stat_reg),
> > +				I915_READ(pp_ctrl_reg));
> >  	}
> >  }
> >  
> > @@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
> >   * is locked
> >   */
> >  
> > -static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
> > +static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
> >  {
> > -	u32	control = I915_READ(PCH_PP_CONTROL);
> > +	struct drm_device *dev = intel_dp->base.base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 control;
> > +	u32 pp_ctrl_reg;
> > +
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +	control = I915_READ(pp_ctrl_reg);
> >  
> >  	control &= ~PANEL_UNLOCK_MASK;
> >  	control |= PANEL_UNLOCK_REGS;
> > @@ -994,6 +1013,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_stat_reg, pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> > @@ -1012,13 +1032,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
> >  	if (!ironlake_edp_have_panel_power(intel_dp))
> >  		ironlake_wait_panel_power_cycle(intel_dp);
> >  
> > -	pp = ironlake_get_pp_control(dev_priv);
> > +	pp = ironlake_get_pp_control(intel_dp);
> >  	pp |= EDP_FORCE_VDD;
> > -	I915_WRITE(PCH_PP_CONTROL, pp);
> > -	POSTING_READ(PCH_PP_CONTROL);
> > -	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> > -		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
> >  
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +
> > +	I915_WRITE(pp_ctrl_reg, pp);
> > +	POSTING_READ(pp_ctrl_reg);
> > +	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> > +			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
> >  	/*
> >  	 * If the panel wasn't on, delay before accessing aux channel
> >  	 */
> > @@ -1033,17 +1056,21 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_stat_reg, pp_ctrl_reg;
> >  
> >  	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
> > -		pp = ironlake_get_pp_control(dev_priv);
> > +		pp = ironlake_get_pp_control(intel_dp);
> >  		pp &= ~EDP_FORCE_VDD;
> > -		I915_WRITE(PCH_PP_CONTROL, pp);
> > -		POSTING_READ(PCH_PP_CONTROL);
> >  
> > -		/* Make sure sequencer is idle before allowing subsequent activity */
> > -		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> > -			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
> > +		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> > +		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> >  
> > +		I915_WRITE(pp_ctrl_reg, pp);
> > +		POSTING_READ(pp_ctrl_reg);
> > +
> > +		/* Make sure sequencer is idle before allowing subsequent activity */
> > +		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> > +		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
> >  		msleep(intel_dp->panel_power_down_delay);
> >  	}
> >  }
> > @@ -1087,6 +1114,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> > @@ -1100,7 +1128,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> >  
> >  	ironlake_wait_panel_power_cycle(intel_dp);
> >  
> > -	pp = ironlake_get_pp_control(dev_priv);
> > +	pp = ironlake_get_pp_control(intel_dp);
> >  	if (IS_GEN5(dev)) {
> >  		/* ILK workaround: disable reset around power sequence */
> >  		pp &= ~PANEL_POWER_RESET;
> > @@ -1112,8 +1140,10 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> >  	if (!IS_GEN5(dev))
> >  		pp |= PANEL_POWER_RESET;
> >  
> > -	I915_WRITE(PCH_PP_CONTROL, pp);
> > -	POSTING_READ(PCH_PP_CONTROL);
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +
> > +	I915_WRITE(pp_ctrl_reg, pp);
> > +	POSTING_READ(pp_ctrl_reg);
> >  
> >  	ironlake_wait_panel_on(intel_dp);
> >  
> > @@ -1129,6 +1159,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> > @@ -1137,12 +1168,15 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
> >  
> >  	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
> >  
> > -	pp = ironlake_get_pp_control(dev_priv);
> > +	pp = ironlake_get_pp_control(intel_dp);
> >  	/* We need to switch off panel power _and_ force vdd, for otherwise some
> >  	 * panels get very unhappy and cease to work. */
> >  	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
> > -	I915_WRITE(PCH_PP_CONTROL, pp);
> > -	POSTING_READ(PCH_PP_CONTROL);
> > +
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +
> > +	I915_WRITE(pp_ctrl_reg, pp);
> > +	POSTING_READ(pp_ctrl_reg);
> >  
> >  	intel_dp->want_panel_vdd = false;
> >  
> > @@ -1154,6 +1188,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> > @@ -1166,10 +1201,13 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> >  	 * allowing it to appear.
> >  	 */
> >  	msleep(intel_dp->backlight_on_delay);
> > -	pp = ironlake_get_pp_control(dev_priv);
> > +	pp = ironlake_get_pp_control(intel_dp);
> >  	pp |= EDP_BLC_ENABLE;
> > -	I915_WRITE(PCH_PP_CONTROL, pp);
> > -	POSTING_READ(PCH_PP_CONTROL);
> > +
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +
> > +	I915_WRITE(pp_ctrl_reg, pp);
> > +	POSTING_READ(pp_ctrl_reg);
> >  }
> >  
> >  static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> > @@ -1177,15 +1215,17 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 pp;
> > +	u32 pp_ctrl_reg;
> >  
> >  	if (!is_edp(intel_dp))
> >  		return;
> >  
> >  	DRM_DEBUG_KMS("\n");
> > -	pp = ironlake_get_pp_control(dev_priv);
> > +	pp = ironlake_get_pp_control(intel_dp);
> >  	pp &= ~EDP_BLC_ENABLE;
> > -	I915_WRITE(PCH_PP_CONTROL, pp);
> > -	POSTING_READ(PCH_PP_CONTROL);
> > +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> > +	I915_WRITE(pp_ctrl_reg, pp);
> > +	POSTING_READ(pp_ctrl_reg);
> >  	msleep(intel_dp->backlight_off_delay);
> >  }
> >  
> > @@ -2547,9 +2587,15 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> >  		u32 pp_on, pp_off, pp_div;
> >  		struct edid *edid;
> >  
> > -		pp_on = I915_READ(PCH_PP_ON_DELAYS);
> > -		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> > -		pp_div = I915_READ(PCH_PP_DIVISOR);
> > +		if (IS_VALLEYVIEW(dev)) {
> > +			pp_on = I915_READ(PIPEA_PP_ON_DELAYS);
> > +			pp_off = I915_READ(PIPEA_PP_OFF_DELAYS);
> > +			pp_div = I915_READ(PIPEA_PP_DIVISOR);
> > +		} else {
> > +			pp_on = I915_READ(PCH_PP_ON_DELAYS);
> > +			pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> > +			pp_div = I915_READ(PCH_PP_DIVISOR);
> > +		}
> >  
> >  		if (!pp_on || !pp_off || !pp_div) {
> >  			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
> 
> I think Daniel's right that it would be good to abstract this a bit.
> Pretty sure people are building machines with multiple embedded panels
> and using some i2c interface for doing the secondary sequence.  A good
> abstraction would help with that too.

I'll happily reiterate that I prefer abstraction once we actually have
more than one user, so I don't mind merging this here ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 5/9] drm/i915: Disable CRT hotplug detection for valleyview

[Daniel Vetter]

On Thu, Sep 27, 2012 at 08:20:15AM -0700, Jesse Barnes wrote:
> On Thu, 27 Sep 2012 19:13:05 +0530
> Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:
> 
> > Temporary work around to avoid spurious crt hotplug interrupts.
> > 
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_crt.c |    7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index c42b980..5f30364 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> >  	bool ret;
> >  	u32 save_adpa;
> >  
> > +	/*
> > +	 * Disable crt detect hotplug for VLV X0. Spurious hot plug
> > +	 * detect calls crashses the X0 system
> > +	 */
> > +	if (IS_VALLEYVIEW(dev))
> > +		return false;
> > +
> >  	save_adpa = adpa = I915_READ(ADPA);
> >  	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
> >  
> 
> Not sure about this one; your platform seems to be less stable than
> mine when it comes to both VGA port handling and legacy VGA I/O...  But
> I have no problem with it either, I just know it works ok on at least
> some of the SDVs, probably depending on board rework and firmware
> status.
> 
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Since it's unclear whether we need this, I'll punt on this patch here.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview

[Daniel Vetter]

On Thu, Sep 27, 2012 at 08:23:37AM -0700, Jesse Barnes wrote:
> On Thu, 27 Sep 2012 19:13:06 +0530
> Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:
> 
> > In valleyview voltageswing, pre-emphasis and lane control registers can
> > be programmed only through the h/w side band fabric.
> > 
> > Cleaned up DPLL calculations for Valleyview to support multi display
> > configurations.
> > 
> > v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
> > patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
> > i9xx_update_pll.
> > 
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>

Small bikeshed: I've killed some spurious whitespace changs while
applying ...
-Daniel

> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |    8 +--
> >  drivers/gpu/drm/i915/intel_display.c |   90 ++++++++++++++++++++++++----------
> >  2 files changed, 66 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3f75ee6..0fe4aad 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -385,12 +385,8 @@
> >  
> >  #define DPIO_FASTCLK_DISABLE		0x8100
> >  
> > -#define _DPIO_DATA_LANE0		0x0220
> > -#define _DPIO_DATA_LANE1		0x0420
> > -#define _DPIO_DATA_LANE2		0x2620
> > -#define _DPIO_DATA_LANE3		0x2820
> > -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> > -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> > +#define DPIO_DATA_CHANNEL1		0x8220
> > +#define DPIO_DATA_CHANNEL2		0x8420
> >  
> >  /*
> >   * Fence registers
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 68828e7..ed749c4 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> >  			   struct drm_display_mode *mode,
> >  			   struct drm_display_mode *adjusted_mode,
> >  			   intel_clock_t *clock, intel_clock_t *reduced_clock,
> > -			   int refclk, int num_connectors)
> > +			   int num_connectors)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> >  	int pipe = intel_crtc->pipe;
> >  	u32 dpll, mdiv, pdiv;
> >  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> > -	bool is_hdmi;
> > +	bool is_sdvo;
> > +	u32 temp;
> > +
> > +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> > +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> >  
> > -	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> > +	dpll = DPLL_VGA_MODE_DIS;
> > +	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> > +	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> > +	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> > +
> > +	I915_WRITE(DPLL(pipe), dpll);
> > +	POSTING_READ(DPLL(pipe));
> >  
> >  	bestn = clock->n;
> >  	bestm1 = clock->m1;
> > @@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> >  	bestp1 = clock->p1;
> >  	bestp2 = clock->p2;
> >  
> > -	/* Enable DPIO clock input */
> > -	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> > -		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
> > -	I915_WRITE(DPLL(pipe), dpll);
> > -	POSTING_READ(DPLL(pipe));
> > -
> > +	/*
> > +	 * In Valleyview PLL and program lane counter registers are exposed
> > +	 * through DPIO interface
> > +	 */
> >  	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> >  	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> >  	mdiv |= ((bestn << DPIO_N_SHIFT));
> > @@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> >  
> >  	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
> >  
> > -	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> > +	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
> >  		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> > -		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> > +		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
> > +		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
> >  	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
> >  
> > -	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> > +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
> >  
> >  	dpll |= DPLL_VCO_ENABLE;
> >  	I915_WRITE(DPLL(pipe), dpll);
> > @@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> >  	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> >  		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> >  
> > -	if (is_hdmi) {
> > -		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> > +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> > +
> > +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> > +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> > +
> > +	I915_WRITE(DPLL(pipe), dpll);
> > +
> > +	/* Wait for the clocks to stabilize. */
> > +	POSTING_READ(DPLL(pipe));
> > +	udelay(150);
> >  
> > +	temp = 0;
> > +	if (is_sdvo) {
> > +		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> >  		if (temp > 1)
> >  			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> >  		else
> >  			temp = 0;
> > -
> > -		I915_WRITE(DPLL_MD(pipe), temp);
> > -		POSTING_READ(DPLL_MD(pipe));
> >  	}
> > +	I915_WRITE(DPLL_MD(pipe), temp);
> > +	POSTING_READ(DPLL_MD(pipe));
> >  
> > -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
> > +	/* Now program lane control registers */
> > +	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
> > +			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> > +	{
> > +		temp = 0x1000C4;
> > +		if(pipe == 1)
> > +			temp |= (1 << 21);
> > +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
> > +	}
> > +	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
> > +	{
> > +		temp = 0x1000C4;
> > +		if(pipe == 1)
> > +			temp |= (1 << 21);
> > +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
> > +	}
> >  }
> >  
> > +
> >  static void i9xx_update_pll(struct drm_crtc *crtc,
> >  			    struct drm_display_mode *mode,
> >  			    struct drm_display_mode *adjusted_mode,
> > @@ -4092,9 +4127,10 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> >  	u32 dpll;
> >  	bool is_sdvo;
> >  
> > +	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
> > +
> >  	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> >  		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> > -
> >  	dpll = DPLL_VGA_MODE_DIS;
> >  
> >  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> > @@ -4192,7 +4228,7 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> >  
> >  static void i8xx_update_pll(struct drm_crtc *crtc,
> >  			    struct drm_display_mode *adjusted_mode,
> > -			    intel_clock_t *clock,
> > +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
> >  			    int num_connectors)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> > @@ -4201,6 +4237,8 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
> >  	int pipe = intel_crtc->pipe;
> >  	u32 dpll;
> >  
> > +	i9xx_update_pll_dividers(crtc, clock, reduced_clock);
> > +
> >  	dpll = DPLL_VGA_MODE_DIS;
> >  
> >  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> > @@ -4327,14 +4365,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >  	if (is_sdvo && is_tv)
> >  		i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
> >  
> > -	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
> > -				 &reduced_clock : NULL);
> > -
> >  	if (IS_GEN2(dev))
> > -		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> > +		i8xx_update_pll(crtc, adjusted_mode, &clock,
> > +				has_reduced_clock ? &reduced_clock : NULL,
> > +				num_connectors);
> >  	else if (IS_VALLEYVIEW(dev))
> > -		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
> > -			       refclk, num_connectors);
> > +		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
> > +				has_reduced_clock ? &reduced_clock : NULL,
> > +				num_connectors);
> >  	else
> >  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> >  				has_reduced_clock ? &reduced_clock : NULL,
> 
> Looks good.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 7/9] drm/i915: Add eDP support for Valleyview

[Daniel Vetter]

On Thu, Sep 27, 2012 at 08:24:46AM -0700, Jesse Barnes wrote:
> On Thu, 27 Sep 2012 19:13:07 +0530
> Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:
> 
> > From: Gajanan Bhat <gajanan.bhat@intel.com>
> > 
> > Eventhough Valleyview display block is derived from Cantiga, VLV
> > supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> > 
> > v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> > v3: fix DPIO value calculation to use same values for all display
> > interfaces
> > v4: removed unconditional enabling of 6bpc dithering based on comments
> > from Daniel & Jani Nikula. Also changed the display enabling order to
> > force eDP detection first.
> > 
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>

Ok, I've slurped in the patches with the exception of the vga detect quirk
(maybe that'll go away with the hpd rework anyway) and the panel stuff
(since no one volunteered yet to smash an r-b onto it).

For the edp stuff here I think we need to add a bit more abstraction
eventually - maybe add an enum of the different kinds of DP connectors
(cpu, fdi, gmch) or add some vtable interfaces for the things which are
different on different platforms/ports ...

Thanks, Daniel

> > ---
> >  drivers/gpu/drm/i915/intel_display.c |   15 ++++++++++++---
> >  drivers/gpu/drm/i915/intel_dp.c      |   17 ++++++++++++-----
> >  2 files changed, 24 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ed749c4..0362c80 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4413,6 +4413,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >  		}
> >  	}
> >  
> > +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> > +		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> > +			pipeconf |= PIPECONF_BPP_6 |
> > +					PIPECONF_ENABLE |
> > +					I965_PIPECONF_ACTIVE;
> > +		}
> > +	}
> > +
> >  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
> >  	drm_mode_debug_printmodeline(mode);
> >  
> > @@ -7623,6 +7631,10 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  	} else if (IS_VALLEYVIEW(dev)) {
> >  		int found;
> >  
> > +		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
> > +		if (I915_READ(DP_C) & DP_DETECTED)
> > +			intel_dp_init(dev, DP_C, PORT_C);
> > +
> >  		if (I915_READ(SDVOB) & PORT_DETECTED) {
> >  			/* SDVOB multiplex with HDMIB */
> >  			found = intel_sdvo_init(dev, SDVOB, true);
> > @@ -7635,9 +7647,6 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  		if (I915_READ(SDVOC) & PORT_DETECTED)
> >  			intel_hdmi_init(dev, SDVOC, PORT_C);
> >  
> > -		/* Shares lanes with HDMI on SDVOC */
> > -		if (I915_READ(DP_C) & DP_DETECTED)
> > -			intel_dp_init(dev, DP_C, PORT_C);
> >  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> >  		bool found = false;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index c111c3f..867c568 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> >  
> >  	/* Split out the IBX/CPU vs CPT settings */
> >  
> > -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> > +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> >  			intel_dp->DP |= DP_SYNC_HS_HIGH;
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> > @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  
> > -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> >  		case DP_TRAIN_VOLTAGE_SWING_400:
> >  			return DP_TRAIN_PRE_EMPHASIS_6;
> > @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >  		uint32_t    signal_levels;
> >  
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >  			break;
> >  		}
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -2471,7 +2471,14 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> >  		if (intel_dpd_is_edp(dev))
> >  			intel_dp->is_pch_edp = true;
> >  
> > -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> > +	/*
> > +	 * FIXME : We need to initialize built-in panels before external panels.
> > +	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
> > +	 */
> > +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> > +		type = DRM_MODE_CONNECTOR_eDP;
> > +		intel_encoder->type = INTEL_OUTPUT_EDP;
> > +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> >  		type = DRM_MODE_CONNECTOR_eDP;
> >  		intel_encoder->type = INTEL_OUTPUT_EDP;
> >  	} else {
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch