* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
@ 2012-10-27 13:28 Andrew Lunn
2012-10-27 16:31 ` Linus Walleij
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Andrew Lunn @ 2012-10-27 13:28 UTC (permalink / raw)
To: linux-arm-kernel
Due to the SMP nature of some of the chips, which have per CPU
registers, the driver does not use the generic irq_gc_mask_set_bit() &
irq_gc_mask_clr_bit() functions, which only support a single register.
The driver has its own implementation of these functions, which can
pick the correct register depending on the CPU being used. The
functions do however use the gc->mask_cache value.
The call to irq_setup_generic_chip() was passing
IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
initialized to the contents of some random register. This resulted in
unexpected interrupts been delivered from random GPIO lines.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/gpio/gpio-mvebu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index eb42ab1..cf7afb9 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -646,7 +646,7 @@ static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
ct->handler = handle_edge_irq;
ct->chip.name = mvchip->chip.label;
- irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+ irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
/* Setup irq domain on top of the generic chip. */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
2012-10-27 13:28 [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache Andrew Lunn
@ 2012-10-27 16:31 ` Linus Walleij
2012-10-27 16:53 ` Thomas Petazzoni
2012-10-28 12:17 ` Jamie Lentin
2012-10-28 16:33 ` Michael Walle
2 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2012-10-27 16:31 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 27, 2012 at 3:28 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> Due to the SMP nature of some of the chips, which have per CPU
> registers, the driver does not use the generic irq_gc_mask_set_bit() &
> irq_gc_mask_clr_bit() functions, which only support a single register.
> The driver has its own implementation of these functions, which can
> pick the correct register depending on the CPU being used. The
> functions do however use the gc->mask_cache value.
>
> The call to irq_setup_generic_chip() was passing
> IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
> initialized to the contents of some random register. This resulted in
> unexpected interrupts been delivered from random GPIO lines.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Thanks, patch applied to fixes. Unless Thomas screams...
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
2012-10-27 16:31 ` Linus Walleij
@ 2012-10-27 16:53 ` Thomas Petazzoni
2012-10-27 16:58 ` Andrew Lunn
0 siblings, 1 reply; 6+ messages in thread
From: Thomas Petazzoni @ 2012-10-27 16:53 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 27 Oct 2012 18:31:41 +0200, Linus Walleij wrote:
> On Sat, Oct 27, 2012 at 3:28 PM, Andrew Lunn <andrew@lunn.ch> wrote:
>
> > Due to the SMP nature of some of the chips, which have per CPU
> > registers, the driver does not use the generic irq_gc_mask_set_bit() &
> > irq_gc_mask_clr_bit() functions, which only support a single register.
> > The driver has its own implementation of these functions, which can
> > pick the correct register depending on the CPU being used. The
> > functions do however use the gc->mask_cache value.
> >
> > The call to irq_setup_generic_chip() was passing
> > IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
> > initialized to the contents of some random register. This resulted in
> > unexpected interrupts been delivered from random GPIO lines.
> >
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
>
> Thanks, patch applied to fixes. Unless Thomas screams...
Acked-by-the-not-screaming: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Sounds good? :-)
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
2012-10-27 16:53 ` Thomas Petazzoni
@ 2012-10-27 16:58 ` Andrew Lunn
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Lunn @ 2012-10-27 16:58 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 27, 2012 at 06:53:05PM +0200, Thomas Petazzoni wrote:
>
> On Sat, 27 Oct 2012 18:31:41 +0200, Linus Walleij wrote:
> > On Sat, Oct 27, 2012 at 3:28 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > Due to the SMP nature of some of the chips, which have per CPU
> > > registers, the driver does not use the generic irq_gc_mask_set_bit() &
> > > irq_gc_mask_clr_bit() functions, which only support a single register.
> > > The driver has its own implementation of these functions, which can
> > > pick the correct register depending on the CPU being used. The
> > > functions do however use the gc->mask_cache value.
> > >
> > > The call to irq_setup_generic_chip() was passing
> > > IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
> > > initialized to the contents of some random register. This resulted in
> > > unexpected interrupts been delivered from random GPIO lines.
> > >
> > > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> >
> > Thanks, patch applied to fixes. Unless Thomas screams...
>
> Acked-by-the-not-screaming: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>
> Sounds good? :-)
https://lwn.net/Articles/503829
Its at least new...
Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
2012-10-27 13:28 [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache Andrew Lunn
2012-10-27 16:31 ` Linus Walleij
@ 2012-10-28 12:17 ` Jamie Lentin
2012-10-28 16:33 ` Michael Walle
2 siblings, 0 replies; 6+ messages in thread
From: Jamie Lentin @ 2012-10-28 12:17 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 27 Oct 2012, Andrew Lunn wrote:
> Due to the SMP nature of some of the chips, which have per CPU
> registers, the driver does not use the generic irq_gc_mask_set_bit() &
> irq_gc_mask_clr_bit() functions, which only support a single register.
> The driver has its own implementation of these functions, which can
> pick the correct register depending on the CPU being used. The
> functions do however use the gc->mask_cache value.
>
> The call to irq_setup_generic_chip() was passing
> IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
> initialized to the contents of some random register. This resulted in
> unexpected interrupts been delivered from random GPIO lines.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
This is what was causing my NAS to lock up when I turned the LEDs off.
Thanks! The only one not working now is the power LED, patch coming soon
to fix that.
> ---
> drivers/gpio/gpio-mvebu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
> index eb42ab1..cf7afb9 100644
> --- a/drivers/gpio/gpio-mvebu.c
> +++ b/drivers/gpio/gpio-mvebu.c
> @@ -646,7 +646,7 @@ static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
> ct->handler = handle_edge_irq;
> ct->chip.name = mvchip->chip.label;
>
> - irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
> + irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
> IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
>
> /* Setup irq domain on top of the generic chip. */
>
--
Jamie Lentin
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache
2012-10-27 13:28 [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache Andrew Lunn
2012-10-27 16:31 ` Linus Walleij
2012-10-28 12:17 ` Jamie Lentin
@ 2012-10-28 16:33 ` Michael Walle
2 siblings, 0 replies; 6+ messages in thread
From: Michael Walle @ 2012-10-28 16:33 UTC (permalink / raw)
To: linux-arm-kernel
Am Samstag 27 Oktober 2012, 15:28:58 schrieb Andrew Lunn:
> Due to the SMP nature of some of the chips, which have per CPU
> registers, the driver does not use the generic irq_gc_mask_set_bit() &
> irq_gc_mask_clr_bit() functions, which only support a single register.
> The driver has its own implementation of these functions, which can
> pick the correct register depending on the CPU being used. The
> functions do however use the gc->mask_cache value.
>
> The call to irq_setup_generic_chip() was passing
> IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
> initialized to the contents of some random register. This resulted in
> unexpected interrupts been delivered from random GPIO lines.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> drivers/gpio/gpio-mvebu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
> index eb42ab1..cf7afb9 100644
> --- a/drivers/gpio/gpio-mvebu.c
> +++ b/drivers/gpio/gpio-mvebu.c
> @@ -646,7 +646,7 @@ static int __devinit mvebu_gpio_probe(struct
> platform_device *pdev) ct->handler = handle_edge_irq;
> ct->chip.name = mvchip->chip.label;
>
> - irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
> + irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
> IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
>
> /* Setup irq domain on top of the generic chip. */
Tested-by: Michael Walle <michael@walle.cc>
Fixes my lock ups when booting, too.
--
Michael
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-10-28 16:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-10-27 13:28 [PATCH] GPIO: mvebu-gpio: Don't initialize the mask_cache Andrew Lunn
2012-10-27 16:31 ` Linus Walleij
2012-10-27 16:53 ` Thomas Petazzoni
2012-10-27 16:58 ` Andrew Lunn
2012-10-28 12:17 ` Jamie Lentin
2012-10-28 16:33 ` Michael Walle
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