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From: Daniel Vetter <daniel@ffwll.ch>
To: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix HSW power well control state read
Date: Tue, 30 Oct 2012 20:37:46 +0100	[thread overview]
Message-ID: <20121030193746.GC5755@phenom.ffwll.local> (raw)
In-Reply-To: <1351595794-4378-1-git-send-email-zhenyuw@linux.intel.com>

On Tue, Oct 30, 2012 at 07:16:34PM +0800, Zhenyu Wang wrote:
> Fix power well control state by reading real register offset.
> 
> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

      reply	other threads:[~2012-10-30 19:36 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-30 11:16 [PATCH] drm/i915: Fix HSW power well control state read Zhenyu Wang
2012-10-30 19:37 ` Daniel Vetter [this message]

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