From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: "Antti Koskipää" <antti.koskipaa@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
Date: Thu, 1 Nov 2012 07:50:19 -0700 [thread overview]
Message-ID: <20121101075019.3fcde501@jbarnes-desktop> (raw)
In-Reply-To: <50928BB1.3060904@linux.intel.com>
On Thu, 01 Nov 2012 16:48:17 +0200
Antti Koskipää <antti.koskipaa@linux.intel.com> wrote:
> Hi,
>
> On 10/25/12 22:15, Jesse Barnes wrote:
> > This allows us to get the right vblank interrupt frequency.
> >
> > v2: pull in register definition
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6464eaa..4aec0a3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -556,6 +556,8 @@
> > #define IIR 0x020a4
> > #define IMR 0x020a8
> > #define ISR 0x020ac
> > +#define VLV_GUNIT_CLOCK_GATE 0x182060
>
> Where did you pull this offset from? It's not in the Bspec.
No, it's in the gunit spec. I'm still working on getting that one
opened up.
--
Jesse Barnes, Intel Open Source Technology Center
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next prev parent reply other threads:[~2012-11-01 14:50 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-25 19:15 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-25 19:15 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-11-01 14:48 ` Antti Koskipää
2012-11-01 14:50 ` Jesse Barnes [this message]
2012-11-01 14:52 ` Antti Koskipää
2012-10-25 19:15 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Jesse Barnes
2012-10-26 11:13 ` Chris Wilson
2012-10-26 16:42 ` Jesse Barnes
2012-11-02 12:41 ` Chris Wilson
2012-10-25 19:15 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-25 19:15 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-11-02 15:34 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2012-10-18 18:07 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-18 15:43 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging " Jesse Barnes
2012-10-18 15:43 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
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