From: Chris Wilson <chris@chris-wilson.co.uk>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op
Date: Fri, 02 Nov 2012 12:41:00 +0000 [thread overview]
Message-ID: <eeac1e$4s5ff9@AZSMGA002.ch.intel.com> (raw)
In-Reply-To: <20121026094242.0c74d329@jbarnes-desktop>
On Fri, 26 Oct 2012 09:42:42 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> commit b99c792eddf804150b3341a85c256df50d7ab5c2
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Sep 19 13:02:39 2012 -0700
>
> drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
>
> So store into the scratch space of the HWS to make sure the invalidate
> occurs.
>
> v2: use GTT address space for store, clean up #defines (Chris)
> v3: use correct #define in blt ring flush (Chris)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
That looks to be the code I executed, but I can't confirm it fixes any
problems.
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
which looks to be a likely victim of a missing TLB flush on the blitter
ring.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-11-02 12:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-25 19:15 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-25 19:15 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-11-01 14:48 ` Antti Koskipää
2012-11-01 14:50 ` Jesse Barnes
2012-11-01 14:52 ` Antti Koskipää
2012-10-25 19:15 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Jesse Barnes
2012-10-26 11:13 ` Chris Wilson
2012-10-26 16:42 ` Jesse Barnes
2012-11-02 12:41 ` Chris Wilson [this message]
2012-10-25 19:15 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-25 19:15 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-11-02 15:34 ` Daniel Vetter
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