[Qemu-devel] [PATCH v1 0/3] Xilinx Microblaze IP updates

[Qemu-devel] [PATCH v1 0/3] Xilinx Microblaze IP updates

[Peter Crosthwaite]

Minor fixes to xilinx microblaze IP.

Peter Crosthwaite (3):
  xilinx_axienet: Implement R_IS behaviour
  xilinx_uartlite: suppress "cannot receive message"
  xilinx_uartlite: Accept input after rx FIFO pop

 hw/xilinx_axienet.c  |    4 ++++
 hw/xilinx_uartlite.c |    7 ++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

[Qemu-devel] [PATCH v1 1/3] xilinx_axienet: Implement R_IS behaviour

[Peter Crosthwaite]

The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/xilinx_axienet.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index baae02b..f2e3bf1 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr,
             s->maddr[s->fmi & 3][addr & 1] = value;
             break;
 
+        case R_IS:
+            s->regs[addr] &= ~value;
+            break;
+
         case 0x8000 ... 0x83ff:
             s->ext_mtable[addr - 0x8000] = value;
             break;
-- 
1.7.0.4

[Qemu-devel] [PATCH v1 2/3] xilinx_uartlite: suppress "cannot receive message"

[Peter Crosthwaite]

This message is not an error condition, its just informing the user that
the device is corking the uart traffic to not drop characters.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/xilinx_uartlite.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index d20fc41..f890f23 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -182,12 +182,8 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
 static int uart_can_rx(void *opaque)
 {
     struct xlx_uartlite *s = opaque;
-    int r;
 
-    r = s->rx_fifo_len < sizeof(s->rx_fifo);
-    if (!r)
-        printf("cannot receive!\n");
-    return r;
+    return s->rx_fifo_len < sizeof(s->rx_fifo);
 }
 
 static void uart_event(void *opaque, int event)
-- 
1.7.0.4

[Qemu-devel] [PATCH v1 3/3] xilinx_uartlite: Accept input after rx FIFO pop

[Peter Crosthwaite]

The device return false from the can receive function when the FIFO is
full. This mean the device should check for buffered input whenever a byte is
popped from the FIFO.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/xilinx_uartlite.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index f890f23..02c5850 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -97,6 +97,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
                 s->rx_fifo_len--;
             uart_update_status(s);
             uart_update_irq(s);
+            qemu_chr_accept_input(s->chr);
             break;
 
         default:
-- 
1.7.0.4

Re: [Qemu-devel] [PATCH v1 0/3] Xilinx Microblaze IP updates

[Edgar E. Iglesias]

On Wed, Dec 05, 2012 at 04:53:41PM +1000, Peter Crosthwaite wrote:
> Minor fixes to xilinx microblaze IP.
> 
> Peter Crosthwaite (3):
>   xilinx_axienet: Implement R_IS behaviour
>   xilinx_uartlite: suppress "cannot receive message"
>   xilinx_uartlite: Accept input after rx FIFO pop
> 
>  hw/xilinx_axienet.c  |    4 ++++
>  hw/xilinx_uartlite.c |    7 ++-----
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 


Applied all, thanks Peter.