* Re: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."
2012-12-18 9:50 [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Jayachandran C
@ 2012-12-18 18:27 ` David Daney
2012-12-18 18:39 ` Hill, Steven
2012-12-19 5:18 ` Hill, Steven
1 sibling, 1 reply; 5+ messages in thread
From: David Daney @ 2012-12-18 18:27 UTC (permalink / raw)
To: Jayachandran C, ralf; +Cc: Steven J . Hill, linux-mips
On 12/18/2012 01:50 AM, Jayachandran C wrote:
> This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e.
>
> The commit causes a boot-time crash on Netlogic XLP boards. The
> crash is caused by the second part of the patch that changes
> build_get_ptep(), which seems to break mips64 TLB handling on r2
> platforms.
>
> Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Acked-by: David Daney <david.daney@cavium.com>
The offending patch is incorrect and should be reverted. It uses EXT
and INS on 64-bit values.
David Daney
> ---
> arch/mips/mm/tlbex.c | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index e085e15..1a17a9b 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -976,13 +976,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
> #endif
> uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
> uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
> -
> - if (cpu_has_mips_r2) {
> - uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT));
> - uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT));
> - return;
> - }
> -
> uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
> uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
> uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
> @@ -1018,15 +1011,6 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
>
> static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
> {
> - if (cpu_has_mips_r2) {
> - /* PTE ptr offset is obtained from BadVAddr */
> - UASM_i_MFC0(p, tmp, C0_BADVADDR);
> - UASM_i_LW(p, ptr, 0, ptr);
> - uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
> - uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
> - return;
> - }
> -
> /*
> * Bug workaround for the Nevada. It seems as if under certain
> * circumstances the move from cp0_context might produce a
>
^ permalink raw reply [flat|nested] 5+ messages in thread* RE: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."
2012-12-18 9:50 [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Jayachandran C
2012-12-18 18:27 ` David Daney
@ 2012-12-19 5:18 ` Hill, Steven
2012-12-19 9:02 ` Jayachandran C.
1 sibling, 1 reply; 5+ messages in thread
From: Hill, Steven @ 2012-12-19 5:18 UTC (permalink / raw)
To: Jayachandran C, ralf@linux-mips.org; +Cc: linux-mips@linux-mips.org
[-- Attachment #1: Type: text/plain, Size: 162 bytes --]
JC,
Can you try to apply this patch on top of the "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." patch and let me know of the results. Thanks.
-Steve
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: fix-optimise-tlb-for-mips64r2.patch --]
[-- Type: text/x-patch; name="fix-optimise-tlb-for-mips64r2.patch", Size: 4333 bytes --]
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 53542e3c..761fa18 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -893,7 +893,7 @@ enum mm_major_op {
mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
- mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
+ mm_ori32_op, mm_pool32f_op, mm_pools32s_op, mm_reserved2_op,
mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
@@ -1095,6 +1095,18 @@ enum mm_32f_73_minor_op {
};
/*
+ * POOL32S minor opcodes.
+ */
+enum mm_32s_minor_op {
+ mm_dinsm_op = 0x04,
+ mm_dins_op = 0x0c,
+ mm_dextu_op = 0x14,
+ mm_dextm_op = 0x24,
+ mm_dext_op = 0x2c,
+ mm_dinsu_op = 0x34,
+};
+
+/*
* POOL16C minor opcodes.
*/
enum mm_16c_minor_op {
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 2a6c65a..70bf8f1 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -77,6 +77,7 @@ Ip_u1u2s3(_bne);
Ip_u2s3u1(_cache);
Ip_u2u1s3(_daddiu);
Ip_u3u1u2(_daddu);
+Ip_u2u1msbu3(_dext);
Ip_u2u1msbu3(_dins);
Ip_u2u1msbu3(_dinsm);
Ip_u1u2u3(_dmfc0);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d50e6d1..699e352 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1088,8 +1088,13 @@ static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr
/* PTE ptr offset is obtained from BadVAddr */
UASM_i_MFC0(p, tmp, C0_BADVADDR);
UASM_i_LW(p, ptr, 0, ptr);
+#ifdef CONFIG_CPU_MIPS64
+ uasm_i_dext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
+ uasm_i_dins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
+#else
uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
+#endif
return;
}
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index f2b834a..1d3067e 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -37,6 +37,9 @@ static struct insn insn_table[] __uasminitdata = {
{ insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
{ insn_daddu, 0, 0 },
{ insn_daddiu, 0, 0 },
+ { insn_dext, M(mm_pools32s_op, 0, 0, 0, 0, mm_dext_op), RS | RT | RD | RE},
+ { insn_dins, M(mm_pools32s_op, 0, 0, 0, 0, mm_dins_op), RS | RT | RD | RE},
+ { insn_dinsm, M(mm_pools32s_op, 0, 0, 0, 0, mm_dinsm_op), RS | RT | RD | RE},
{ insn_dmfc0, 0, 0 },
{ insn_dmtc0, 0, 0 },
{ insn_dsll, 0, 0 },
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index e86334b..2695076 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -37,6 +37,8 @@ static struct insn insn_table[] __uasminitdata = {
{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_dext, M(spec3_op, 0, 0, 0, 0, dext_op), RS | RT | RD | RE},
+ { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index d3b01b90..65725be 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -68,7 +68,7 @@ enum opcode {
insn_invalid,
insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
- insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
+ insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dext, insn_dins, insn_dinsm,
insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
@@ -309,6 +309,7 @@ I_0(_tlbwi)
I_0(_tlbwr)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
+I_u2u1msbdu3(_dext)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);
^ permalink raw reply related [flat|nested] 5+ messages in thread