* [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
@ 2013-02-20 20:39 Jiri Olsa
2013-02-20 20:55 ` Andi Kleen
0 siblings, 1 reply; 6+ messages in thread
From: Jiri Olsa @ 2013-02-20 20:39 UTC (permalink / raw)
To: linux-kernel
Cc: Jiri Olsa, Arnaldo Carvalho de Melo, Namhyung Kim, Corey Ashford,
Frederic Weisbecker, Ingo Molnar, Paul Mackerras, Peter Zijlstra,
Andi Kleen, David Ahern, Stephane Eranian
Changing the default 'instructions' HW event for SandyBridge and
IvyBrige to use the available precise 'instructions' event.
The precise event is defined in Intel SDM as:
INST_RETIRED.ALL - Precise instruction retired event with HW to
reduce effect of PEBS shadow in IP distribution
for both SandyBridge and IvyBrige micro-archs. It allows to use
precise modifier on 'instructions' event on SandyBridge and
IvyBrige micro-archs which is not possible now.
Signed-off-by: Jiri Olsa <jolsa@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: David Ahern <dsahern@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 529c893..3bc3592 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2104,6 +2104,9 @@ __init int intel_pmu_init(void)
/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
+ /* INST_RETIRED.ALL to count precise instructions */
+ intel_perfmon_event_map[PERF_COUNT_HW_INSTRUCTIONS] =
+ X86_CONFIG(.event=0xc0, .umask=0x01);
pr_cont("SandyBridge events, ");
break;
@@ -2127,6 +2130,9 @@ __init int intel_pmu_init(void)
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+ /* INST_RETIRED.ALL to count precise instructions */
+ intel_perfmon_event_map[PERF_COUNT_HW_INSTRUCTIONS] =
+ X86_CONFIG(.event=0xc0, .umask=0x01);
pr_cont("IvyBridge events, ");
break;
--
1.7.11.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
2013-02-20 20:39 [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise Jiri Olsa
@ 2013-02-20 20:55 ` Andi Kleen
2013-02-20 21:01 ` Stephane Eranian
2013-02-20 21:18 ` Jiri Olsa
0 siblings, 2 replies; 6+ messages in thread
From: Andi Kleen @ 2013-02-20 20:55 UTC (permalink / raw)
To: Jiri Olsa
Cc: linux-kernel, Arnaldo Carvalho de Melo, Namhyung Kim,
Corey Ashford, Frederic Weisbecker, Ingo Molnar, Paul Mackerras,
Peter Zijlstra, David Ahern, Stephane Eranian
Jiri Olsa <jolsa@redhat.com> writes:
> Changing the default 'instructions' HW event for SandyBridge and
> IvyBrige to use the available precise 'instructions' event.
>
> The precise event is defined in Intel SDM as:
>
> INST_RETIRED.ALL - Precise instruction retired event with HW to
> reduce effect of PEBS shadow in IP distribution
>
> for both SandyBridge and IvyBrige micro-archs. It allows to use
> precise modifier on 'instructions' event on SandyBridge and
> IvyBrige micro-archs which is not possible now.
Actually it's possible, you just have to use it explicitely.
This will break a lot of profiling setups that assume instructions
count on the fixed counter and use the 4/8 other counters.
Also it will give very bad results with perf stat, which
you don't want to run with pebs.
Even worse with your change the fixed instruction counter is not
accessible anymore. So pretty much all the standard setups
that collect it in addition to other events and fill all
the counters would break.
I don't think it should be done by default, but yes explicitely
it's quite useful.
My Haswell patchkit (in the "extended version") exposes
the precise event as "instructions-p" through sysfs.
-Andi
--
ak@linux.intel.com -- Speaking for myself only
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
2013-02-20 20:55 ` Andi Kleen
@ 2013-02-20 21:01 ` Stephane Eranian
2013-02-20 21:29 ` Jiri Olsa
2013-02-20 21:48 ` Andi Kleen
2013-02-20 21:18 ` Jiri Olsa
1 sibling, 2 replies; 6+ messages in thread
From: Stephane Eranian @ 2013-02-20 21:01 UTC (permalink / raw)
To: Andi Kleen
Cc: Jiri Olsa, LKML, Arnaldo Carvalho de Melo, Namhyung Kim,
Corey Ashford, Frederic Weisbecker, Ingo Molnar, Paul Mackerras,
Peter Zijlstra, David Ahern
On Wed, Feb 20, 2013 at 9:55 PM, Andi Kleen <andi@firstfloor.org> wrote:
> Jiri Olsa <jolsa@redhat.com> writes:
>
>> Changing the default 'instructions' HW event for SandyBridge and
>> IvyBrige to use the available precise 'instructions' event.
>>
>> The precise event is defined in Intel SDM as:
>>
>> INST_RETIRED.ALL - Precise instruction retired event with HW to
>> reduce effect of PEBS shadow in IP distribution
>>
>> for both SandyBridge and IvyBrige micro-archs. It allows to use
>> precise modifier on 'instructions' event on SandyBridge and
>> IvyBrige micro-archs which is not possible now.
>
There is also the problem that on SNB, PREC_DIST must be
taken ALONE to be correct. By that, I mean no other counter
must be active. So I don't think it is a good idea.
Also PREC_DIST is marked as constrained to counter 2 only.
That in effect, as Andi pointed out, will make the fixed counter
for instruction_retired, unused because you've set a umask now.
I don't think it buys you much. People read too much into what
PEBS gives you. I can show you examples where PEBS
is worse than no PEBS.
> Actually it's possible, you just have to use it explicitely.
>
> This will break a lot of profiling setups that assume instructions
> count on the fixed counter and use the 4/8 other counters.
> Also it will give very bad results with perf stat, which
> you don't want to run with pebs.
>
> Even worse with your change the fixed instruction counter is not
> accessible anymore. So pretty much all the standard setups
> that collect it in addition to other events and fill all
> the counters would break.
>
> I don't think it should be done by default, but yes explicitely
> it's quite useful.
>
> My Haswell patchkit (in the "extended version") exposes
> the precise event as "instructions-p" through sysfs.
>
> -Andi
>
> --
> ak@linux.intel.com -- Speaking for myself only
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
2013-02-20 21:01 ` Stephane Eranian
@ 2013-02-20 21:29 ` Jiri Olsa
2013-02-20 21:48 ` Andi Kleen
1 sibling, 0 replies; 6+ messages in thread
From: Jiri Olsa @ 2013-02-20 21:29 UTC (permalink / raw)
To: Stephane Eranian
Cc: Andi Kleen, LKML, Arnaldo Carvalho de Melo, Namhyung Kim,
Corey Ashford, Frederic Weisbecker, Ingo Molnar, Paul Mackerras,
Peter Zijlstra, David Ahern
On Wed, Feb 20, 2013 at 10:01:20PM +0100, Stephane Eranian wrote:
> On Wed, Feb 20, 2013 at 9:55 PM, Andi Kleen <andi@firstfloor.org> wrote:
> > Jiri Olsa <jolsa@redhat.com> writes:
> >
> >> Changing the default 'instructions' HW event for SandyBridge and
> >> IvyBrige to use the available precise 'instructions' event.
> >>
> >> The precise event is defined in Intel SDM as:
> >>
> >> INST_RETIRED.ALL - Precise instruction retired event with HW to
> >> reduce effect of PEBS shadow in IP distribution
> >>
> >> for both SandyBridge and IvyBrige micro-archs. It allows to use
> >> precise modifier on 'instructions' event on SandyBridge and
> >> IvyBrige micro-archs which is not possible now.
> >
> There is also the problem that on SNB, PREC_DIST must be
> taken ALONE to be correct. By that, I mean no other counter
> must be active. So I don't think it is a good idea.
>
> Also PREC_DIST is marked as constrained to counter 2 only.
> That in effect, as Andi pointed out, will make the fixed counter
> for instruction_retired, unused because you've set a umask now.
>
> I don't think it buys you much. People read too much into what
> PEBS gives you. I can show you examples where PEBS
> is worse than no PEBS.
well, we sort of advertise we have precise event via precise
modifier and it confused me I was not able to use it on
IvyBridge..
maybe we could export precise alias in sysfs as well which we
could check & use any time there's 'p' modifier specified
not pretty.. meeds more thinking ;-)
thanks,
jirka
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
2013-02-20 21:01 ` Stephane Eranian
2013-02-20 21:29 ` Jiri Olsa
@ 2013-02-20 21:48 ` Andi Kleen
1 sibling, 0 replies; 6+ messages in thread
From: Andi Kleen @ 2013-02-20 21:48 UTC (permalink / raw)
To: Stephane Eranian
Cc: Andi Kleen, Jiri Olsa, LKML, Arnaldo Carvalho de Melo,
Namhyung Kim, Corey Ashford, Frederic Weisbecker, Ingo Molnar,
Paul Mackerras, Peter Zijlstra, David Ahern
> I don't think it buys you much. People read too much into what
> PEBS gives you. I can show you examples where PEBS
> is worse than no PEBS.
Nothing is perfect in sampling, but the precise instructions event
is definitely better in a range of situations. It avoids
a lot of shadow effects.
I think it's a good choice for a lot of situations, although
on Ivy Bridge without EventingRip the BB walking is still
fairly expensive.
It would be a good default for the "user only asks for instructions
for sampling and nothing else" situation, especially on Haswell
which has EventingRip. But that's not straight forward to detect.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise
2013-02-20 20:55 ` Andi Kleen
2013-02-20 21:01 ` Stephane Eranian
@ 2013-02-20 21:18 ` Jiri Olsa
1 sibling, 0 replies; 6+ messages in thread
From: Jiri Olsa @ 2013-02-20 21:18 UTC (permalink / raw)
To: Andi Kleen
Cc: linux-kernel, Arnaldo Carvalho de Melo, Namhyung Kim,
Corey Ashford, Frederic Weisbecker, Ingo Molnar, Paul Mackerras,
Peter Zijlstra, David Ahern, Stephane Eranian
On Wed, Feb 20, 2013 at 12:55:59PM -0800, Andi Kleen wrote:
> Jiri Olsa <jolsa@redhat.com> writes:
>
> > Changing the default 'instructions' HW event for SandyBridge and
> > IvyBrige to use the available precise 'instructions' event.
> >
> > The precise event is defined in Intel SDM as:
> >
> > INST_RETIRED.ALL - Precise instruction retired event with HW to
> > reduce effect of PEBS shadow in IP distribution
> >
> > for both SandyBridge and IvyBrige micro-archs. It allows to use
> > precise modifier on 'instructions' event on SandyBridge and
> > IvyBrige micro-archs which is not possible now.
>
> Actually it's possible, you just have to use it explicitely.
>
> This will break a lot of profiling setups that assume instructions
> count on the fixed counter and use the 4/8 other counters.
> Also it will give very bad results with perf stat, which
> you don't want to run with pebs.
right, I haven't realized that..
>
> Even worse with your change the fixed instruction counter is not
> accessible anymore. So pretty much all the standard setups
still could be used explicitly via cpu/event=0xc0/
> that collect it in addition to other events and fill all
> the counters would break.
>
> I don't think it should be done by default, but yes explicitely
> it's quite useful.
>
> My Haswell patchkit (in the "extended version") exposes
> the precise event as "instructions-p" through sysfs.
will check
thanks,
jirka
^ permalink raw reply [flat|nested] 6+ messages in thread
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2013-02-20 20:39 [PATCH] perf x86: Change SandyBridge and IvyBrige instructions event to be precise Jiri Olsa
2013-02-20 20:55 ` Andi Kleen
2013-02-20 21:01 ` Stephane Eranian
2013-02-20 21:29 ` Jiri Olsa
2013-02-20 21:48 ` Andi Kleen
2013-02-20 21:18 ` Jiri Olsa
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