Re: [Intel-gfx] [PATCH] drm/i915: Handle untiled planes when computing their offsets

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Feb 21, 2013 at 02:45:26PM +0000, Chris Wilson wrote:
> We trim the fb to fit the CRTC by computing the offset of that CRTC to
> its nearest tile_row origin. This allows us to use framebuffers that are
> larger than the CRTC limits without additional work.
> 
> However, we failed to compute the offset for a linear framebuffer
> correctly as we treated its x-advance in whole tiles (instead of the
> linear increment expected), leaving the CRTC misaligned with its
> contents.
> 
> Fixes regression from commit c2c75131244507c93f812862fdbd4f3a37139401
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date:   Thu Jul 5 12:17:30 2012 +0200
> 
>     drm/i915: adjust framebuffer base address on gen4+
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61152
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: stable@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/intel_display.c |   14 +++++++++-----
>  drivers/gpu/drm/i915/intel_drv.h     |    3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |    6 ++++--
>  3 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a3ca9a8..2a46f08 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1906,18 +1906,20 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
>  
>  /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
>   * is assumed to be a power-of-two. */
> -unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
> +unsigned long intel_gen4_compute_planar_offset(int *x, int *y,
> +					       unsigned int tiling_mode,
>  					       unsigned int bpp,
>  					       unsigned int pitch)
>  {
> -	int tile_rows, tiles;
> +	int tile_rows, tiles, tile_size;
>  
>  	tile_rows = *y / 8;
>  	*y %= 8;
>  	tiles = *x / (512/bpp);
>  	*x %= 512/bpp;
>  
> -	return tile_rows * pitch * 8 + tiles * 4096;
> +	tile_size = tiling_mode != I915_TILING_NONE ? 4096 : 512;
> +	return (tile_rows * pitch * 8 + tiles * tile_size) & -4096;

This doesn't seem to work as intended. Eg. plug in
x=128, y=0, bpp=4, pitch=1024 and you get x=0,y=0,off=0 out.

Well I suppose it works when we actually have the LINOFF register since
we compute the value using the original x/y values, and the subtract the
result from this computation. But that sort of behaviour seems a bit
fragile. And in any case, this won't work on HSW where we use the
adjusted x/y offsets even w/ linear surfaces.

-- 
Ville Syrjälä
Intel OTC