From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Daniel Vetter <daniel@ffwll.ch>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: GFDT support for SNB/IVB
Date: Mon, 4 Mar 2013 15:51:11 +0200 [thread overview]
Message-ID: <20130304135111.GH4469@intel.com> (raw)
In-Reply-To: <20130303173908.GB5364@cantiga.alporthouse.com>
On Sun, Mar 03, 2013 at 05:39:09PM +0000, Chris Wilson wrote:
> On Sun, Mar 03, 2013 at 05:28:52PM +0100, Daniel Vetter wrote:
> > The other thing was that I didn't manage to get things to work properly,
> > leaving some random cachline dirt on the screen. Looking at your code, you
> > add the gfdt flush to every ring_flush, whereas I've tried to be clever
> > and only flushed after batches rendering to the frontbuffer. So probably a
> > bug in my code, or a flush on a given ring doesn't flush out caches for
> > one of the other engines.
>
> Right, we have a formalized interface for flushes to scanout rather than
> always flushing GFDT.
We do? Where's that?
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-03-04 13:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-01 18:32 [PATCH] drm/i915: GFDT support for SNB/IVB ville.syrjala
2013-03-03 16:28 ` Daniel Vetter
2013-03-03 17:39 ` Chris Wilson
2013-03-04 13:51 ` Ville Syrjälä [this message]
2013-03-04 14:01 ` Chris Wilson
2013-03-04 14:03 ` Ville Syrjälä
2013-03-06 16:28 ` Chris Wilson
2013-04-04 9:01 ` Daniel Vetter
2013-04-04 11:27 ` Ville Syrjälä
2013-04-04 12:17 ` Chris Wilson
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