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From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
To: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Fabio Estevam
	<fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
	spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages
Date: Tue, 2 Apr 2013 12:32:12 +0200	[thread overview]
Message-ID: <201304021232.12736.marex@denx.de> (raw)
In-Reply-To: <CA+7tXigvg+5k0Baa12CVwP5Ar7HUsJ8ihB19xrav4CNA6ZMFiA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

Dear Trent Piepho,

> On Mon, Apr 1, 2013 at 9:22 PM, Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> wrote:
> >> On Mon, Apr 1, 2013 at 4:11 PM, Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> wrote:
> >> >> +#define TXRX_WRITE           1       /* This is a write */
> >> >> +#define TXRX_DEASSERT_CS     2       /* De-assert CS at end of txrx
> >> >> */
> > 
> > btw. is it necessary to define new flags or is it possible to reuse some?
> 
> I don't see any others that would make sense.  The driver doesn't
> define any flags at all.  The spi layer doesn't have ones that match.
> And this is for a private static interface inside the driver.  It
> wouldn't be right to co-opt flags defined for some other purpose.

Ok, makes sense then.

btw. if defining bitfield flags, it makes more sense to use (1 << n) notation to 
make it more readable and also less prone to people using the actual flag value 
as a bitshift argument.

> >> >>       ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
> >> >> 
> >> >> -     ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
> >> >> +     ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT & ~BM_SSP_CTRL0_IGNORE_CRC &
> >> >> +              ~BM_SSP_CTRL0_READ;
> >> > 
> >> > Well ... ctrl0 &= ~(FOO | BAR | BAZ); ... won't cut it?
> >> 
> >> Well, by De Morgan's law the two expressions are the same.  And they
> >> are the same number of characters.  And both will produce a compile
> >> time constant and thus the same code.  However, I like the ~FOO & ~BAR
> >> & ~BAR form better as there is greater parallelism between each term
> >> of the expression.
> > 
> > What about the law of readability of code ? ;-)
> 
> Don't see anything in CodingStyle that one should be preferred over
> the other.

There ain't any I'm aware of, but to paraphrase you, let's keep the format 
that's already used in the driver ;-) :

114         if (dev->mode & ~(SPI_CPOL | SPI_CPHA))

> I think this way is more readable than the other.
> Generally you can think of masking off bits via bitwise-and and
> setting bits with bitwise-or.  So if you want to do a sequence of
> masks, then using a sequence of bitwise-ands is the most readable and
> straightforward code IMHO.  Combing bits to mask with bitwise-or, then
> inverting the set and masking with that seems like a less clear way of
> doing the same thing.  And this way the existing tokens aren't
> modified, so there is less churn!
> 
> >> The DMA does write
> >> ctrl0 on each segment of each transfer, but look at the previous
> >> paragraph to see where it comes from.  Once READ or IGNORE_CRC are
> >> set, nothing will clear them until PIO mode is used.
> > 
> > When using a flash, the DMA and PIO mode usage is intermixed. Usually,
> > the PIO is used to program the command and then DMA to transmit the
> > payload. It's hardly ever PIO only orr DMA only for the whole transfer.
> 
> Probably why the problem hasn't been noticed.  It's obvious from a
> cursory examination of the driver that bits in ctrl0 are only SET in
> the DMA code, never cleared.  The PIO code does clear them.
> 
> >> It's the same
> >> with the bug fix for 3.9 that clears the XFER_COUNT bits in DMA mode.
> >> Strangely, I didn't notice that bug since all my xfers are the same
> >> length!  But I do switch between slaves, between read and write, and
> >> use messages with multiple transfers, in DMA mode, all of which are
> >> broken in the current driver.
> > 
> > btw. are you using MX23 or MX28 to test this?
> 
> IMX28.

Is that any mainline board?

> >> Existing code that uses the first/last flags is wrong and needs to be
> >> changed.  Therefor code using 'first' and 'last' will be changed.
> >> 
> >> Passing the flags as pointers is bad practice and makes no sense to
> >> do.  Does it make any sense to re-write code fix the way it uses first
> >> and last, then re-write those same lines a second time to not use
> >> pointers?
> > 
> > You can always flip it the other way -- first rework the use of flags,
> > then apply the fix. It'd make the patch much easier to understand, don't
> > you think?
> 
> So I should change 'first' to not be a pointer to an integer in one
> patch, then delete the flag entirely in another patch?

I'd say make a patch (0001) that implements the transition to using your newly 
defined flags and then make a patch (0002) that "Fix extra CS pulses and read 
mode in multi-transfer messages". One patch shall do one thing, that's the usual 
rule of the thumb. Obviously keep them in a series if these patches shall go in 
together. And why doesn't squashing them all together work you might ask -- 
because reviewing the result is hard.

[...]

Best regards,
Marek Vasut

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WARNING: multiple messages have this Message-ID (diff)
From: marex@denx.de (Marek Vasut)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages
Date: Tue, 2 Apr 2013 12:32:12 +0200	[thread overview]
Message-ID: <201304021232.12736.marex@denx.de> (raw)
In-Reply-To: <CA+7tXigvg+5k0Baa12CVwP5Ar7HUsJ8ihB19xrav4CNA6ZMFiA@mail.gmail.com>

Dear Trent Piepho,

> On Mon, Apr 1, 2013 at 9:22 PM, Marek Vasut <marex@denx.de> wrote:
> >> On Mon, Apr 1, 2013 at 4:11 PM, Marek Vasut <marex@denx.de> wrote:
> >> >> +#define TXRX_WRITE           1       /* This is a write */
> >> >> +#define TXRX_DEASSERT_CS     2       /* De-assert CS at end of txrx
> >> >> */
> > 
> > btw. is it necessary to define new flags or is it possible to reuse some?
> 
> I don't see any others that would make sense.  The driver doesn't
> define any flags at all.  The spi layer doesn't have ones that match.
> And this is for a private static interface inside the driver.  It
> wouldn't be right to co-opt flags defined for some other purpose.

Ok, makes sense then.

btw. if defining bitfield flags, it makes more sense to use (1 << n) notation to 
make it more readable and also less prone to people using the actual flag value 
as a bitshift argument.

> >> >>       ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
> >> >> 
> >> >> -     ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
> >> >> +     ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT & ~BM_SSP_CTRL0_IGNORE_CRC &
> >> >> +              ~BM_SSP_CTRL0_READ;
> >> > 
> >> > Well ... ctrl0 &= ~(FOO | BAR | BAZ); ... won't cut it?
> >> 
> >> Well, by De Morgan's law the two expressions are the same.  And they
> >> are the same number of characters.  And both will produce a compile
> >> time constant and thus the same code.  However, I like the ~FOO & ~BAR
> >> & ~BAR form better as there is greater parallelism between each term
> >> of the expression.
> > 
> > What about the law of readability of code ? ;-)
> 
> Don't see anything in CodingStyle that one should be preferred over
> the other.

There ain't any I'm aware of, but to paraphrase you, let's keep the format 
that's already used in the driver ;-) :

114         if (dev->mode & ~(SPI_CPOL | SPI_CPHA))

> I think this way is more readable than the other.
> Generally you can think of masking off bits via bitwise-and and
> setting bits with bitwise-or.  So if you want to do a sequence of
> masks, then using a sequence of bitwise-ands is the most readable and
> straightforward code IMHO.  Combing bits to mask with bitwise-or, then
> inverting the set and masking with that seems like a less clear way of
> doing the same thing.  And this way the existing tokens aren't
> modified, so there is less churn!
> 
> >> The DMA does write
> >> ctrl0 on each segment of each transfer, but look at the previous
> >> paragraph to see where it comes from.  Once READ or IGNORE_CRC are
> >> set, nothing will clear them until PIO mode is used.
> > 
> > When using a flash, the DMA and PIO mode usage is intermixed. Usually,
> > the PIO is used to program the command and then DMA to transmit the
> > payload. It's hardly ever PIO only orr DMA only for the whole transfer.
> 
> Probably why the problem hasn't been noticed.  It's obvious from a
> cursory examination of the driver that bits in ctrl0 are only SET in
> the DMA code, never cleared.  The PIO code does clear them.
> 
> >> It's the same
> >> with the bug fix for 3.9 that clears the XFER_COUNT bits in DMA mode.
> >> Strangely, I didn't notice that bug since all my xfers are the same
> >> length!  But I do switch between slaves, between read and write, and
> >> use messages with multiple transfers, in DMA mode, all of which are
> >> broken in the current driver.
> > 
> > btw. are you using MX23 or MX28 to test this?
> 
> IMX28.

Is that any mainline board?

> >> Existing code that uses the first/last flags is wrong and needs to be
> >> changed.  Therefor code using 'first' and 'last' will be changed.
> >> 
> >> Passing the flags as pointers is bad practice and makes no sense to
> >> do.  Does it make any sense to re-write code fix the way it uses first
> >> and last, then re-write those same lines a second time to not use
> >> pointers?
> > 
> > You can always flip it the other way -- first rework the use of flags,
> > then apply the fix. It'd make the patch much easier to understand, don't
> > you think?
> 
> So I should change 'first' to not be a pointer to an integer in one
> patch, then delete the flag entirely in another patch?

I'd say make a patch (0001) that implements the transition to using your newly 
defined flags and then make a patch (0002) that "Fix extra CS pulses and read 
mode in multi-transfer messages". One patch shall do one thing, that's the usual 
rule of the thumb. Obviously keep them in a series if these patches shall go in 
together. And why doesn't squashing them all together work you might ask -- 
because reviewing the result is hard.

[...]

Best regards,
Marek Vasut

  parent reply	other threads:[~2013-04-02 10:32 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-29 15:19 [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Trent Piepho
2013-03-29 15:19 ` Trent Piepho
     [not found] ` <1364570381-17605-1-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-03-29 15:19   ` [PATCH 2/5] spi/mxs: Fix chip select control bits in DMA mode Trent Piepho
2013-03-29 15:19     ` Trent Piepho
     [not found]     ` <1364570381-17605-2-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:13       ` Marek Vasut
2013-04-01 23:13         ` Marek Vasut
     [not found]         ` <201304020113.42124.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:27           ` Trent Piepho
2013-04-01 23:27             ` Trent Piepho
     [not found]             ` <CA+7tXih2wAVeLpVoYkt4Tmo3h0YtLoZY3vCcv5s8sUD1u8_BVQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-01 23:30               ` Marek Vasut
2013-04-01 23:30                 ` Marek Vasut
     [not found]                 ` <201304020130.51951.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:40                   ` Trent Piepho
2013-04-01 23:40                     ` Trent Piepho
     [not found]                     ` <CA+7tXij_V1iAdPuPoTQ6CK6U5Y-iJprCPsTj=_LHAV1-=CL7gA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  0:02                       ` Marek Vasut
2013-04-02  0:02                         ` Marek Vasut
     [not found]                         ` <201304020202.43501.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  1:58                           ` Trent Piepho
2013-04-02  1:58                             ` Trent Piepho
2013-03-29 15:19   ` [PATCH 3/5] spi/mxs: Remove full duplex check, spi core already does it Trent Piepho
2013-03-29 15:19     ` Trent Piepho
2013-03-29 15:19   ` [PATCH 4/5] spi/mxs: Remove bogus setting of ssp clk rate field Trent Piepho
2013-03-29 15:19     ` Trent Piepho
     [not found]     ` <1364570381-17605-4-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:16       ` Marek Vasut
2013-04-01 23:16         ` Marek Vasut
     [not found]         ` <201304020116.04781.marex-ynQEQJNshbs@public.gmane.org>
2013-04-01 23:32           ` Trent Piepho
2013-04-01 23:32             ` Trent Piepho
     [not found]             ` <CA+7tXihhL2ETT+AgvX5KASZOOgi6bucModE88ztY9Q8U1gDbOQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-01 23:37               ` Marek Vasut
2013-04-01 23:37                 ` Marek Vasut
2013-04-02  0:07                 ` Trent Piepho
2013-04-02  0:07                   ` Trent Piepho
     [not found]                   ` <CA+7tXihfDnmkTJGzk_yvRKYwb5mJzzLJVV+XupCEGnmpQdKDLQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  0:29                     ` Marek Vasut
2013-04-02  0:29                       ` Marek Vasut
2013-03-29 15:19   ` [PATCH 5/5] spi/mxs: Fix multiple slave bug and don't set clock for each xfer Trent Piepho
2013-03-29 15:19     ` Trent Piepho
     [not found]     ` <1364570381-17605-5-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-01 23:18       ` Marek Vasut
2013-04-01 23:18         ` Marek Vasut
2013-04-01 23:11   ` [PATCH 1/5] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Marek Vasut
2013-04-01 23:11     ` Marek Vasut
     [not found]     ` <201304020111.13969.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  1:24       ` Trent Piepho
2013-04-02  1:24         ` Trent Piepho
     [not found]         ` <CA+7tXigx=qcDDJZGAx7JEX+Y-CDG-B0xyYgs6fHbUZofH7gnKw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02  4:22           ` Marek Vasut
2013-04-02  4:22             ` Marek Vasut
     [not found]             ` <201304020622.52429.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02  7:11               ` Trent Piepho
2013-04-02  7:11                 ` Trent Piepho
     [not found]                 ` <CA+7tXigvg+5k0Baa12CVwP5Ar7HUsJ8ihB19xrav4CNA6ZMFiA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02 10:32                   ` Marek Vasut [this message]
2013-04-02 10:32                     ` Marek Vasut
     [not found]                     ` <201304021232.12736.marex-ynQEQJNshbs@public.gmane.org>
2013-04-02 12:40                       ` Trent Piepho
2013-04-02 12:40                         ` Trent Piepho
     [not found]                         ` <CA+7tXii8xhZQeKU2dTN26LxySNXhJT9NgRXcJ21cOX64qYj1NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-02 23:39                           ` Marek Vasut
2013-04-02 23:39                             ` Marek Vasut

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