* [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10
@ 2013-03-29 6:56 ` Simon Horman
0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2013-03-29 6:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Hi Olof,
The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0:
irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10
for you to fetch changes up to 427cc720277c140e6a63a03237f9bf37d8076ac3:
irqchip: intc-irqpin: Add support for shared interrupt lines (2013-03-28 16:39:46 +0900)
----------------------------------------------------------------
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
----------------------------------------------------------------
Bastian Hecht (1):
irqchip: intc-irqpin: Add support for shared interrupt lines
drivers/irqchip/irq-renesas-intc-irqpin.c | 90 ++++++++++++++++++++++++++---
1 file changed, 83 insertions(+), 7 deletions(-)
^ permalink raw reply [flat|nested] 8+ messages in thread* [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 @ 2013-03-29 6:56 ` Simon Horman 0 siblings, 0 replies; 8+ messages in thread From: Simon Horman @ 2013-03-29 6:56 UTC (permalink / raw) To: linux-arm-kernel Hi Arnd, Hi Olof, The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0: irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10 for you to fetch changes up to 427cc720277c140e6a63a03237f9bf37d8076ac3: irqchip: intc-irqpin: Add support for shared interrupt lines (2013-03-28 16:39:46 +0900) ---------------------------------------------------------------- Update for Renesas INTC External IRQ pin driver for v3.10 This adds support for shared interrupt lines to the Renesas INTC External IRQ pin driver which has already been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10). ---------------------------------------------------------------- Bastian Hecht (1): irqchip: intc-irqpin: Add support for shared interrupt lines drivers/irqchip/irq-renesas-intc-irqpin.c | 90 ++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] irqchip: intc-irqpin: Add support for shared interrupt lines 2013-03-29 6:56 ` Simon Horman @ 2013-03-29 6:56 ` Simon Horman -1 siblings, 0 replies; 8+ messages in thread From: Simon Horman @ 2013-03-29 6:56 UTC (permalink / raw) To: linux-arm-kernel From: Bastian Hecht <hechtb@gmail.com> On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- drivers/irqchip/irq-renesas-intc-irqpin.c | 90 ++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index fd5dabc..5a68e5a 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -74,6 +74,8 @@ struct intc_irqpin_priv { struct platform_device *pdev; struct irq_chip irq_chip; struct irq_domain *irq_domain; + bool shared_irqs; + u8 shared_irq_mask; }; static unsigned long intc_irqpin_read32(void __iomem *iomem) @@ -193,6 +195,28 @@ static void intc_irqpin_irq_disable(struct irq_data *d) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); } +static void intc_irqpin_shared_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); + + p->shared_irq_mask &= ~BIT(hw_irq); +} + +static void intc_irqpin_shared_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); + + p->shared_irq_mask |= BIT(hw_irq); +} + static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); @@ -261,6 +285,25 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) return IRQ_NONE; } +static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_priv *p = dev_id; + unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); + irqreturn_t status = IRQ_NONE; + int k; + + for (k = 0; k < 8; k++) { + if (reg_source & BIT(7 - k)) { + if (BIT(k) & p->shared_irq_mask) + continue; + + status |= intc_irqpin_irq_handler(irq, &p->irq[k]); + } + } + + return status; +} + static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { @@ -292,6 +335,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) void (*enable_fn)(struct irq_data *d); void (*disable_fn)(struct irq_data *d); const char *name = dev_name(&pdev->dev); + int ref_irq; int ret; int k; @@ -372,13 +416,29 @@ static int intc_irqpin_probe(struct platform_device *pdev) for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); + /* clear all pending interrupts */ + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); + + /* scan for shared interrupt lines */ + ref_irq = p->irq[0].requested_irq; + p->shared_irqs = true; + for (k = 1; k < p->number_of_irqs; k++) { + if (ref_irq != p->irq[k].requested_irq) { + p->shared_irqs = false; + break; + } + } + /* use more severe masking method if requested */ if (p->config.control_parent) { enable_fn = intc_irqpin_irq_enable_force; disable_fn = intc_irqpin_irq_disable_force; - } else { + } else if (!p->shared_irqs) { enable_fn = intc_irqpin_irq_enable; disable_fn = intc_irqpin_irq_disable; + } else { + enable_fn = intc_irqpin_shared_irq_enable; + disable_fn = intc_irqpin_shared_irq_disable; } irq_chip = &p->irq_chip; @@ -400,18 +460,34 @@ static int intc_irqpin_probe(struct platform_device *pdev) goto err0; } - /* request and set priority on interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (p->shared_irqs) { + /* request one shared interrupt */ + if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, + intc_irqpin_shared_irq_handler, + IRQF_SHARED, name, p)) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; goto err1; } - intc_irqpin_mask_unmask_prio(p, k, 0); + } else { + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (devm_request_irq(&pdev->dev, + p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, + "failed to request low IRQ\n"); + ret = -ENOENT; + goto err1; + } + } } + /* unmask all interrupts on prio level */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 0); + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); /* warn in case of mismatch if irq base is specified */ -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] irqchip: intc-irqpin: Add support for shared interrupt lines @ 2013-03-29 6:56 ` Simon Horman 0 siblings, 0 replies; 8+ messages in thread From: Simon Horman @ 2013-03-29 6:56 UTC (permalink / raw) To: linux-arm-kernel From: Bastian Hecht <hechtb@gmail.com> On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- drivers/irqchip/irq-renesas-intc-irqpin.c | 90 ++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index fd5dabc..5a68e5a 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -74,6 +74,8 @@ struct intc_irqpin_priv { struct platform_device *pdev; struct irq_chip irq_chip; struct irq_domain *irq_domain; + bool shared_irqs; + u8 shared_irq_mask; }; static unsigned long intc_irqpin_read32(void __iomem *iomem) @@ -193,6 +195,28 @@ static void intc_irqpin_irq_disable(struct irq_data *d) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); } +static void intc_irqpin_shared_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); + + p->shared_irq_mask &= ~BIT(hw_irq); +} + +static void intc_irqpin_shared_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); + + p->shared_irq_mask |= BIT(hw_irq); +} + static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); @@ -261,6 +285,25 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) return IRQ_NONE; } +static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_priv *p = dev_id; + unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); + irqreturn_t status = IRQ_NONE; + int k; + + for (k = 0; k < 8; k++) { + if (reg_source & BIT(7 - k)) { + if (BIT(k) & p->shared_irq_mask) + continue; + + status |= intc_irqpin_irq_handler(irq, &p->irq[k]); + } + } + + return status; +} + static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { @@ -292,6 +335,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) void (*enable_fn)(struct irq_data *d); void (*disable_fn)(struct irq_data *d); const char *name = dev_name(&pdev->dev); + int ref_irq; int ret; int k; @@ -372,13 +416,29 @@ static int intc_irqpin_probe(struct platform_device *pdev) for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); + /* clear all pending interrupts */ + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); + + /* scan for shared interrupt lines */ + ref_irq = p->irq[0].requested_irq; + p->shared_irqs = true; + for (k = 1; k < p->number_of_irqs; k++) { + if (ref_irq != p->irq[k].requested_irq) { + p->shared_irqs = false; + break; + } + } + /* use more severe masking method if requested */ if (p->config.control_parent) { enable_fn = intc_irqpin_irq_enable_force; disable_fn = intc_irqpin_irq_disable_force; - } else { + } else if (!p->shared_irqs) { enable_fn = intc_irqpin_irq_enable; disable_fn = intc_irqpin_irq_disable; + } else { + enable_fn = intc_irqpin_shared_irq_enable; + disable_fn = intc_irqpin_shared_irq_disable; } irq_chip = &p->irq_chip; @@ -400,18 +460,34 @@ static int intc_irqpin_probe(struct platform_device *pdev) goto err0; } - /* request and set priority on interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (p->shared_irqs) { + /* request one shared interrupt */ + if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, + intc_irqpin_shared_irq_handler, + IRQF_SHARED, name, p)) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; goto err1; } - intc_irqpin_mask_unmask_prio(p, k, 0); + } else { + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (devm_request_irq(&pdev->dev, + p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, + "failed to request low IRQ\n"); + ret = -ENOENT; + goto err1; + } + } } + /* unmask all interrupts on prio level */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 0); + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); /* warn in case of mismatch if irq base is specified */ -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 2013-03-29 6:56 ` Simon Horman @ 2013-04-08 15:54 ` Arnd Bergmann -1 siblings, 0 replies; 8+ messages in thread From: Arnd Bergmann @ 2013-04-08 15:54 UTC (permalink / raw) To: linux-arm-kernel On Friday 29 March 2013, Simon Horman wrote: > Hi Arnd, Hi Olof, > > The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0: > > irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10 > Pulled into next/drivers, thanks! Sorry for the slight delay in processing this. Arnd ^ permalink raw reply [flat|nested] 8+ messages in thread
* [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 @ 2013-04-08 15:54 ` Arnd Bergmann 0 siblings, 0 replies; 8+ messages in thread From: Arnd Bergmann @ 2013-04-08 15:54 UTC (permalink / raw) To: linux-arm-kernel On Friday 29 March 2013, Simon Horman wrote: > Hi Arnd, Hi Olof, > > The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0: > > irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10 > Pulled into next/drivers, thanks! Sorry for the slight delay in processing this. Arnd ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 2013-04-08 15:54 ` Arnd Bergmann @ 2013-04-08 15:59 ` Arnd Bergmann -1 siblings, 0 replies; 8+ messages in thread From: Arnd Bergmann @ 2013-04-08 15:59 UTC (permalink / raw) To: linux-arm-kernel On Monday 08 April 2013, Arnd Bergmann wrote: > On Friday 29 March 2013, Simon Horman wrote: > > Hi Arnd, Hi Olof, > > > > The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0: > > > > irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900) > > > > are available in the git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10 > > > > Pulled into next/drivers, thanks! > > Sorry for the slight delay in processing this. > Ah, I found now that we already had other branches based on this patch merged into renesas/pinmux2 and renesas/soc2. Anyway, now we have it as a separate branch tag. Arnd ^ permalink raw reply [flat|nested] 8+ messages in thread
* [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 @ 2013-04-08 15:59 ` Arnd Bergmann 0 siblings, 0 replies; 8+ messages in thread From: Arnd Bergmann @ 2013-04-08 15:59 UTC (permalink / raw) To: linux-arm-kernel On Monday 08 April 2013, Arnd Bergmann wrote: > On Friday 29 March 2013, Simon Horman wrote: > > Hi Arnd, Hi Olof, > > > > The following changes since commit 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0: > > > > irqchip: irqc: Add DT support (2013-03-18 21:26:07 +0900) > > > > are available in the git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-intc-external-irq2-for-v3.10 > > > > Pulled into next/drivers, thanks! > > Sorry for the slight delay in processing this. > Ah, I found now that we already had other branches based on this patch merged into renesas/pinmux2 and renesas/soc2. Anyway, now we have it as a separate branch tag. Arnd ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-04-08 15:59 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-03-29 6:56 [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 Simon Horman 2013-03-29 6:56 ` Simon Horman 2013-03-29 6:56 ` [PATCH] irqchip: intc-irqpin: Add support for shared interrupt lines Simon Horman 2013-03-29 6:56 ` Simon Horman 2013-04-08 15:54 ` [GIT PULL] Update for Renesas INTC External IRQ pin driver for v3.10 Arnd Bergmann 2013-04-08 15:54 ` Arnd Bergmann 2013-04-08 15:59 ` Arnd Bergmann 2013-04-08 15:59 ` Arnd Bergmann
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