Re: [Qemu-devel] [PATCH v3 16/27] tcg-ppc64: Implement bswap16 and bswap32

[Aurelien Jarno <aurelien@aurel32.net>]

On Mon, Apr 01, 2013 at 09:23:19PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>  tcg/ppc64/tcg-target.h | 18 ++++++++++--------
>  2 files changed, 53 insertions(+), 8 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index c512714..d8131ec 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1668,6 +1668,44 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>                           const_args[2]);
>          break;
>  
> +    case INDEX_op_bswap16_i32:
> +    case INDEX_op_bswap16_i64:
> +        a0 = args[0], a1 = args[1];
> +        /* a1 = abcd */
> +        if (a0 != a1) {
> +            /* a0 = (a1 r<< 24) & 0xff # 000c */
> +            tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
> +            /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
> +            tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
> +        } else {
> +            /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
> +            tcg_out_rlw(s, RLWINM, 0, a1, 8, 16, 23);
> +            /* a0 = (a1 r<< 24) & 0xff # 000c */
> +            tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
> +            /* a0 = a0 | r0 # 00dc */
> +            tcg_out32(s, OR | SAB(0, a0, a0));
> +        }
> +        break;
> +
> +    case INDEX_op_bswap32_i32:
> +    case INDEX_op_bswap32_i64:
> +        /* Stolen from gcc's builtin_bswap32 */
> +        a1 = args[1];
> +        a0 = args[0] == a1 ? 0 : args[0];
> +
> +        /* a1 = args[1] # abcd */
> +        /* a0 = rotate_left (a1, 8) # bcda */
> +        tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
> +        /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
> +        tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
> +        /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
> +        tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
> +
> +        if (!a0) {
> +            tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
> +        }
> +        break;
> +

It would be a lot easier to read if you had use TCG_REG_R0 instead of 0,
especially for the if.


>      default:
>          tcg_dump_ops (s);
>          tcg_abort ();
> @@ -1774,6 +1812,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_setcond_i32, { "r", "r", "ri" } },
>      { INDEX_op_setcond_i64, { "r", "r", "ri" } },
>  
> +    { INDEX_op_bswap16_i32, { "r", "r" } },
> +    { INDEX_op_bswap16_i64, { "r", "r" } },
> +    { INDEX_op_bswap32_i32, { "r", "r" } },
> +    { INDEX_op_bswap32_i64, { "r", "r" } },
> +
>      { -1 },
>  };
>  
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index dbefe7d..bd011b8 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -67,15 +67,19 @@ typedef enum {
>  #define TCG_TARGET_STACK_ALIGN 16
>  #define TCG_TARGET_CALL_STACK_OFFSET 48
>  
> +/* optional instructions automatically implemented */
> +#define TCG_TARGET_HAS_ext8u_i32        0 /* andi */
> +#define TCG_TARGET_HAS_ext16u_i32       0
> +#define TCG_TARGET_HAS_ext8u_i64        0
> +#define TCG_TARGET_HAS_ext16u_i64       0
> +

That should go in the andi patches, not this one.

>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> -#define TCG_TARGET_HAS_ext8u_i32        0
> -#define TCG_TARGET_HAS_ext16u_i32       0
> -#define TCG_TARGET_HAS_bswap16_i32      0
> -#define TCG_TARGET_HAS_bswap32_i32      0
> +#define TCG_TARGET_HAS_bswap16_i32      1
> +#define TCG_TARGET_HAS_bswap32_i32      1
>  #define TCG_TARGET_HAS_not_i32          1
>  #define TCG_TARGET_HAS_neg_i32          1
>  #define TCG_TARGET_HAS_andc_i32         0
> @@ -95,11 +99,9 @@ typedef enum {
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1
>  #define TCG_TARGET_HAS_ext32s_i64       1
> -#define TCG_TARGET_HAS_ext8u_i64        0
> -#define TCG_TARGET_HAS_ext16u_i64       0
>  #define TCG_TARGET_HAS_ext32u_i64       1
> -#define TCG_TARGET_HAS_bswap16_i64      0
> -#define TCG_TARGET_HAS_bswap32_i64      0
> +#define TCG_TARGET_HAS_bswap16_i64      1
> +#define TCG_TARGET_HAS_bswap32_i64      1
>  #define TCG_TARGET_HAS_bswap64_i64      0
>  #define TCG_TARGET_HAS_not_i64          1
>  #define TCG_TARGET_HAS_neg_i64          1

Besides that the patch looks fine.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net