From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables
Date: Thu, 2 May 2013 16:00:29 +0100 [thread overview]
Message-ID: <20130502150028.GF20730@arm.com> (raw)
In-Reply-To: <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
>
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.
I think the comment is a bit misleading. You actually don't need
kvm_flush_dcache_to_poc() since you already do this in kvm_set_pte()
etc.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"cdall@cs.columbia.edu" <cdall@cs.columbia.edu>,
Will Deacon <Will.Deacon@arm.com>
Subject: Re: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables
Date: Thu, 2 May 2013 16:00:29 +0100 [thread overview]
Message-ID: <20130502150028.GF20730@arm.com> (raw)
In-Reply-To: <1367505542-2231-4-git-send-email-marc.zyngier@arm.com>
On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required if running on a SMP capable platform
> (the HW PTW can snoop other cpus' L1).
>
> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> a no-op for SMP ARMv7.
I think the comment is a bit misleading. You actually don't need
kvm_flush_dcache_to_poc() since you already do this in kvm_set_pte()
etc.
--
Catalin
next prev parent reply other threads:[~2013-05-02 15:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-02 14:38 [PATCH v2 0/5] ARM: KVM: various mmu related fixes for 3.10 Marc Zyngier
2013-05-02 14:38 ` Marc Zyngier
2013-05-02 14:38 ` [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs Marc Zyngier
2013-05-02 14:38 ` Marc Zyngier
2013-05-02 15:13 ` Catalin Marinas
2013-05-02 15:13 ` Catalin Marinas
2013-05-08 10:46 ` Marc Zyngier
2013-05-08 10:46 ` Marc Zyngier
2013-05-02 14:38 ` [PATCH v2 2/5] ARM: KVM: remove dead prototype for __kvm_tlb_flush_vmid Marc Zyngier
2013-05-02 14:38 ` Marc Zyngier
2013-05-02 14:39 ` [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables Marc Zyngier
2013-05-02 14:39 ` Marc Zyngier
2013-05-02 15:00 ` Catalin Marinas [this message]
2013-05-02 15:00 ` Catalin Marinas
2013-05-02 15:03 ` Will Deacon
2013-05-02 15:03 ` Will Deacon
2013-05-02 15:15 ` Christoffer Dall
2013-05-02 15:15 ` Christoffer Dall
2013-05-02 15:17 ` Will Deacon
2013-05-02 15:17 ` Will Deacon
2013-05-13 5:17 ` Christoffer Dall
2013-05-13 5:17 ` Christoffer Dall
2013-05-13 8:58 ` Will Deacon
2013-05-13 8:58 ` Will Deacon
2013-05-14 17:05 ` Christoffer Dall
2013-05-14 17:05 ` Christoffer Dall
2013-05-02 14:39 ` [PATCH v2 4/5] ARM: KVM: get rid of S2_PGD_SIZE Marc Zyngier
2013-05-02 14:39 ` Marc Zyngier
2013-05-02 14:39 ` [PATCH v2 5/5] ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs Marc Zyngier
2013-05-02 14:39 ` Marc Zyngier
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