* [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board.
@ 2013-05-02 7:38 Jingchang Lu
2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Jingchang Lu @ 2013-05-02 7:38 UTC (permalink / raw)
To: linux-arm-kernel
Documentation/devicetree/bindings/clock/mvf600-clock.txt | 180 ++++++++
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mvf600-twr.dts | 80 ++++
arch/arm/boot/dts/mvf600.dtsi | 426 ++++++++++++++++++
arch/arm/mach-imx/Kconfig | 15 +
arch/arm/mach-imx/Makefile | 3 +
arch/arm/mach-imx/clk-mvf.c | 406 +++++++++++++++++
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-mvf600.c | 118 +++++
arch/arm/mach-imx/pit.c | 244 +++++++++++
11 files changed, 2291 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
create mode 100644 arch/arm/boot/dts/mvf600.dtsi
create mode 100644 arch/arm/mach-imx/clk-mvf.c
create mode 100644 arch/arm/mach-imx/mach-mvf600.c
create mode 100644 arch/arm/mach-imx/pit.c
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 7:38 [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Jingchang Lu @ 2013-05-02 7:38 ` Jingchang Lu 2013-05-02 8:52 ` Sascha Hauer ` (3 more replies) 2013-05-02 7:38 ` [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid Jingchang Lu 2013-05-03 2:40 ` [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Shawn Guo 2 siblings, 4 replies; 13+ messages in thread From: Jingchang Lu @ 2013-05-02 7:38 UTC (permalink / raw) To: linux-arm-kernel This patch adds Freescale Vybrid Family platform core definitions, core drivers, including clock, period interrupt timer(PIT), and DTS based machine support with MVF600 Tower development board. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- V2: Use CLOCKSOURCE_OF_DECLARE init timer Add ONESHOT mode support Add more clks definitions on MVF600 soc .../devicetree/bindings/clock/mvf600-clock.txt | 180 +++++++++ arch/arm/mach-imx/Kconfig | 15 + arch/arm/mach-imx/Makefile | 3 + arch/arm/mach-imx/clk-mvf.c | 406 +++++++++++++++++++++ arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/mach-mvf600.c | 118 ++++++ arch/arm/mach-imx/pit.c | 244 +++++++++++++ 7 files changed, 967 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt create mode 100644 arch/arm/mach-imx/clk-mvf.c create mode 100644 arch/arm/mach-imx/mach-mvf600.c create mode 100644 arch/arm/mach-imx/pit.c diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt new file mode 100644 index 0000000..9f8b20e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt @@ -0,0 +1,180 @@ +* Clock bindings for Freescale Vybrid Family + +Required properties: +- compatible: Should be "fsl,mvf-ccm" +- reg: Address and length of the register set +- interrupts: Should contain CCM interrupt +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of MVF600 +clocks and IDs. + + Clock ID + --------------------------- + dummy 0 + sirc_128k 1 + sirc_32k 2 + firc 3 + sxosc 4 + fxosc 5 + fxosc_half 6 + slow_clk 7 + fast_clk 8 + audio_ext 9 + enet_ext 10 + pll1_main_528m 11 + pll1_pfd1_500m 12 + pll1_pfd2_452m 13 + pll1_pfd3_396m 14 + pll1_pfd4_528m 15 + pll2_main_528m 16 + pll2_pfd1_500m 17 + pll2_pfd2_396m 18 + pll2_pfd3_339m 19 + pll2_pfd4_413m 20 + pll3_main_480m 21 + pll3_pfd1_308m 22 + pll3_pfd2_332m 23 + pll3_pfd3_298m 24 + pll3_pfd4_320m 25 + pll4_main 26 + pll5_main 27 + pll6_main 28 + pll3_main_div 29 + pll4_main_div 30 + pll6_main_div 31 + pll1_sw 32 + pll2_sw 33 + sys_sw 34 + ddr_sw 35 + sys_bus_clk 36 + platform_bus_clk 37 + ipg_bus_clk 38 + uart0_clk 39 + uart1_clk 40 + uart2_clk 41 + uart3_clk 42 + uart4_clk 43 + uart5_clk 44 + pit_clk 45 + i2c0_clk 46 + i2c1_clk 47 + i2c2_clk 48 + i2c3_clk 49 + ftm0_ext_sw 50 + ftm0_fix_sw 51 + ftm0_ext_fix_gate 52 + ftm1_ext_sw 53 + ftm1_fix_sw 54 + ftm1_ext_fix_gate 55 + ftm2_ext_sw 56 + ftm2_fix_sw 57 + ftm2_ext_fix_gate 58 + ftm3_ext_sw 59 + ftm3_fix_sw 60 + ftm3_ext_fix_gate 61 + ftm0_clk 62 + ftm1_clk 63 + ftm2_clk 64 + ftm3_clk 65 + enet_50m 66 + enet_25m 67 + enet_clk_sw 68 + enet_clk 69 + enet_ts_sw 70 + enet_ts 71 + dspi0_clk 72 + dspi1_clk 73 + dspi2_clk 74 + dspi3_clk 75 + wdt_clk 76 + esdhc0_sw 77 + esdhc0_gate 78 + esdhc0_div 79 + esdhc0_clk 80 + esdhc1_sw 81 + esdhc1_gate 82 + esdhc1_div 83 + esdhc1_clk 84 + dcu0_sw 85 + dcu0_gate 86 + dcu0_div 87 + dcu0_clk 88 + dcu1_sw 89 + dcu1_gate 90 + dcu1_div 91 + dcu1_clk 92 + esai_sw 93 + esai_gate 94 + esai_div 95 + esai_clk 96 + sai0_sw 97 + sai0_gate 98 + sai0_div 99 + sai0_clk 100 + sai1_sw 101 + sai1_gate 102 + sai1_div 103 + sai1_clk 104 + sai2_sw 105 + sai2_gate 106 + sai2_div 107 + sai2_clk 108 + sai3_sw 109 + sai3_gate 110 + sai3_div 111 + sai3_clk 112 + usbc0_clk 113 + usbc1_clk 114 + qspi0_sw 115 + qspi0_gate 116 + qspi0_x4_div 117 + qspi0_x2_div 118 + qspi0_x1_div 119 + qspi1_sw 120 + qspi1_gate 121 + qspi1_x4_div 122 + qspi1_x2_div 123 + qspi1_x1_div 124 + qspi0_clk 125 + qspi1_clk 126 + nfc_sw 127 + nfc_gate 128 + nfc_pre_div 129 + nfc_frac_div 130 + nfc_inv 131 + nfc_clk 132 + vadc_sw 133 + vadc_gate 134 + vadc_div 135 + vadc_div_half 136 + vadc_clk 137 + adc0_clk 138 + adc1_clk 139 + dac0_clk 140 + dac1_clk 141 + flexcan0_clk 142 + flexcan1_clk 143 + asrc_clk 144 + gpu_sw 145 + gpu_gate 146 + gpu2d_clk 147 + + + +Examples: + +clks: ccm at 4006b000 { + compatible = "fsl,mvf-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; +}; + +uart1: serial at 40028000 { /* UART1 */ + compatible = "fsl,mvf-uart"; + reg = <0x40028000 0x1000>; + interrupts = <0 62 0x04>; + clocks = <&clks 35>; + clock-names = "ipg"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 78f795d..2fb9562 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -819,6 +819,21 @@ config SOC_IMX6Q help This enables support for Freescale i.MX6 Quad processor. +config SOC_MVF600 + bool "Vybrid Family MVF600 support" + select CPU_V7 + select ARM_GIC + select COMMON_CLK + select CLKSRC_OF + select PINCTRL + select PINCTRL_MVF + select PL310_ERRATA_588369 if CACHE_PL310 + select PL310_ERRATA_727915 if CACHE_PL310 + select PL310_ERRATA_769419 if CACHE_PL310 + + help + This enable support for Freescale Vybrid Family VF6xx MPU. + endif source "arch/arm/mach-imx/devices/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index b16eb39..76a2ead 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -112,4 +112,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o +# Vybrid based machines +obj-$(CONFIG_SOC_MVF600) += clk-mvf.o mach-mvf600.o pit.o + obj-y += devices/ diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c new file mode 100644 index 0000000..1467a304 --- /dev/null +++ b/arch/arm/mach-imx/clk-mvf.c @@ -0,0 +1,406 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/time.h> +#include <linux/hrtimer.h> +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/clkdev.h> +#include <linux/regulator/consumer.h> +#include <asm/div64.h> +#include <linux/clk-provider.h> +#include <linux/clk-private.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> + +#include "hardware.h" +#include "common.h" +#include "clk.h" + + +#define CCM_CCR (ccm_base + 0x00) +#define CCM_CSR (ccm_base + 0x04) +#define CCM_CCSR (ccm_base + 0x08) +#define CCM_CACRR (ccm_base + 0x0c) +#define CCM_CSCMR1 (ccm_base + 0x10) +#define CCM_CSCDR1 (ccm_base + 0x14) +#define CCM_CSCDR2 (ccm_base + 0x18) +#define CCM_CSCDR3 (ccm_base + 0x1c) +#define CCM_CSCMR2 (ccm_base + 0x20) +#define CCM_CSCDR4 (ccm_base + 0x24) +#define CCM_CLPCR (ccm_base + 0x2c) +#define CCM_CISR (ccm_base + 0x30) +#define CCM_CIMR (ccm_base + 0x34) +#define CCM_CGPR (ccm_base + 0x3c) +#define CCM_CCGR0 (ccm_base + 0x40) +#define CCM_CCGR1 (ccm_base + 0x44) +#define CCM_CCGR2 (ccm_base + 0x48) +#define CCM_CCGR3 (ccm_base + 0x4c) +#define CCM_CCGR4 (ccm_base + 0x50) +#define CCM_CCGR5 (ccm_base + 0x54) +#define CCM_CCGR6 (ccm_base + 0x58) +#define CCM_CCGR7 (ccm_base + 0x5c) +#define CCM_CCGR8 (ccm_base + 0x60) +#define CCM_CCGR9 (ccm_base + 0x64) +#define CCM_CCGR10 (ccm_base + 0x68) +#define CCM_CCGR11 (ccm_base + 0x6C) +#define CCM_CMEOR0 (ccm_base + 0x70) +#define CCM_CMEOR1 (ccm_base + 0x74) +#define CCM_CMEOR2 (ccm_base + 0x78) +#define CCM_CMEOR3 (ccm_base + 0x7C) +#define CCM_CMEOR4 (ccm_base + 0x80) +#define CCM_CMEOR5 (ccm_base + 0x84) +#define CCM_CPPDSR (ccm_base + 0x88) +#define CCM_CCOWR (ccm_base + 0x8C) +#define CCM_CCPGR0 (ccm_base + 0x90) +#define CCM_CCPGR1 (ccm_base + 0x94) +#define CCM_CCPGR2 (ccm_base + 0x98) +#define CCM_CCPGR3 (ccm_base + 0x9C) + +#define CCM_CCGRx_CGn(n) (n * 2) + +#define PFD_528SYS_BASE (anatop_base + 0x2B0) +#define PFD_528_BASE (anatop_base + 0x100) +#define PFD_USB_BASE (anatop_base + 0xF0) /* pll3 pfd definition */ + + +static void __iomem *anatop_base; +static void __iomem *ccm_base; + +/* This is used multiple times */ +static const char const *fast_clk_sel[] = { "firc", "fxosc", }; +static const char const *slow_clk_sel[] = { "sirc_32k", "sxosc", }; +static const char const *pll1_pfd_sel[] = { + "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", +}; +static const char const *pll2_pfd_sel[] = { + "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", +}; +static const char const *sys_clk_sel[] = { + "fast_clk", "slow_clk", "pll2_sw", "pll2_main", "pll1_sw", "pll3_main", +}; +static const char const *ddr_clk_sel[] = { "pll2_pfd2", "sys_clk", }; +static const char const *rmii_clk_sel[] = { + "enet_ext", "audio_ext", "enet_50m", "enet_25m", +}; +static const char const *enet_ts_clk_sel[] = { + "enet_ext", "fxosc", "audio_ext", "usb_clk", "enet_ts_clk", "enet_25m", "enet_50m", +}; +static const char const *esai_clk_sel[] = { + "audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div", +}; +static const char const *sai_clk_sel[] = { + "audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div", +}; +static const char const *nfc_clk_sel[] = { + "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", +}; +static const char const *qspi_clk_sel[] = { + "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", +}; +static const char const *esdhc_clk_sel[] = { + "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", +}; +static const char const *dcu_clk_sel[] = { "pll1_pfd2", "pll3_main", }; +static const char const *gpu_clk_sel[] = { "pll2_pfd2", "pll3_pfd2", }; +static const char const *vadc_clk_sel[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; +/* FTM counter clock source, not module clock */ +static const char const *ftm_ext_clk_sel[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; +static const char const *ftm_fix_clk_sel[] = { "sxosc", "ipg_bus", }; + +enum mvf_clks { + dummy, + sirc_128k, sirc_32k, firc, sxosc, fxosc, fxosc_half, + slow_clk, fast_clk, audio_ext, enet_ext, + pll1_main_528m, pll1_pfd1_500m, pll1_pfd2_452m, + pll1_pfd3_396m, pll1_pfd4_528m, pll2_main_528m, pll2_pfd1_500m, + pll2_pfd2_396m, pll2_pfd3_339m, pll2_pfd4_413m, pll3_main_480m, + pll3_pfd1_308m, pll3_pfd2_332m, pll3_pfd3_298m, pll3_pfd4_320m, + pll4_main, pll5_main, pll6_main, + pll3_main_div, pll4_main_div, pll6_main_div, + pll1_sw, pll2_sw, sys_sw, ddr_sw, + sys_bus_clk, platform_bus_clk, ipg_bus_clk, + uart0_clk, uart1_clk, uart2_clk, uart3_clk, uart4_clk, uart5_clk, + pit_clk, + i2c0_clk, i2c1_clk, i2c2_clk, i2c3_clk, + ftm0_ext_sw, ftm0_fix_sw, ftm0_ext_fix_gate, + ftm1_ext_sw, ftm1_fix_sw, ftm1_ext_fix_gate, + ftm2_ext_sw, ftm2_fix_sw, ftm2_ext_fix_gate, + ftm3_ext_sw, ftm3_fix_sw, ftm3_ext_fix_gate, + ftm0_clk, ftm1_clk, ftm2_clk, ftm3_clk, + enet_50m, enet_25m, enet_clk_sw, enet_clk, enet_ts_sw, enet_ts, + dspi0_clk, dspi1_clk, dspi2_clk, dspi3_clk, + wdt_clk, + esdhc0_sw, esdhc0_gate, esdhc0_div, esdhc0_clk, + esdhc1_sw, esdhc1_gate, esdhc1_div, esdhc1_clk, + dcu0_sw, dcu0_gate, dcu0_div, dcu0_clk, + dcu1_sw, dcu1_gate, dcu1_div, dcu1_clk, + esai_sw, esai_gate, esai_div, esai_clk, + sai0_sw, sai0_gate, sai0_div, sai0_clk, + sai1_sw, sai1_gate, sai1_div, sai1_clk, + sai2_sw, sai2_gate, sai2_div, sai2_clk, + sai3_sw, sai3_gate, sai3_div, sai3_clk, + usbc0_clk, usbc1_clk, + qspi0_sw, qspi0_gate, qspi0_x4_div, qspi0_x2_div, qspi0_x1_div, + qspi1_sw, qspi1_gate, qspi1_x4_div, qspi1_x2_div, qspi1_x1_div, + qspi0_clk, qspi1_clk, + nfc_sw, nfc_gate, nfc_pre_div, nfc_frac_div, nfc_inv, nfc_clk, + vadc_sw, vadc_gate, vadc_div, vadc_div_half, vadc_clk, + adc0_clk, adc1_clk, dac0_clk, dac1_clk, + flexcan0_clk, flexcan1_clk, + asrc_clk, + gpu_sw, gpu_gate, gpu2d_clk, + clk_max +}; + +static struct clk_div_table pll4_main_div_table[] = { + [0] = {.val = 0, .div = 1}, + [1] = {.val = 1, .div = 2}, + [2] = {.val = 2, .div = 6}, + [3] = {.val = 3, .div = 8}, + [4] = {.val = 4, .div = 10}, + [5] = {.val = 5, .div = 12}, + [6] = {.val = 6, .div = 14}, + [7] = {.val = 7, .div = 16}, +}; +static struct clk *clk[clk_max]; +static struct clk_onecell_data clk_data; + +int __init mvf_clocks_init(void) +{ + struct device_node *np; + + clk[dummy] = imx_clk_fixed("dummy", 0); + clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */ + clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */ + clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */ + clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */ + + for_each_compatible_node(np, NULL, "fixed-clock") { + u32 rate; + + if (of_property_read_u32(np, "clock-frequency", &rate)) + continue; + else if (of_device_is_compatible(np, "fsl,mvf-osc")) + clk[fxosc] = imx_clk_fixed("fxosc", rate); + else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk")) + clk[audio_ext] = imx_clk_fixed("audio_ext", rate); + else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk")) + clk[enet_ext] = imx_clk_fixed("enet_ext", rate); + } + + /* default to 24Mhz OSC */ + if (!clk[fxosc]) + clk[fxosc] = imx_clk_fixed("fxosc", 24000000); + + clk[fxosc_half] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-anatop"); + anatop_base = of_iomap(np, 0); + WARN_ON(!anatop_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-ccm"); + ccm_base = of_iomap(np, 0); + WARN_ON(!ccm_base); + + clk[slow_clk] = imx_clk_mux("slow_clk", CCM_CCSR, 4, 1, + slow_clk_sel, ARRAY_SIZE(slow_clk_sel)); + clk[fast_clk] = imx_clk_mux("fast_clk", CCM_CCSR, 5, 1, + fast_clk_sel, ARRAY_SIZE(fast_clk_sel)); + + clk[pll1_main_528m] = imx_clk_fixed_factor("pll1_main", "fast_clk", 22, 1); + clk[pll1_pfd1_500m] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_528SYS_BASE, 0); + clk[pll1_pfd2_452m] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_528SYS_BASE, 1); + clk[pll1_pfd3_396m] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_528SYS_BASE, 2); + clk[pll1_pfd4_528m] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_528SYS_BASE, 3); + + clk[pll2_main_528m] = imx_clk_fixed_factor("pll2_main", "fast_clk", 22, 1); + clk[pll2_pfd1_500m] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_528_BASE, 0); + clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_528_BASE, 1); + clk[pll2_pfd3_339m] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_528_BASE, 2); + clk[pll2_pfd4_413m] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_528_BASE, 3); + + clk[pll3_main_480m] = imx_clk_fixed_factor("pll3_main", "fast_clk", 20, 1); + clk[pll4_main] = imx_clk_fixed_factor("pll4_main", "fast_clk", 25, 1); + /* Enet pll: fixed 50Mhz */ + clk[pll5_main] = imx_clk_fixed_factor("pll5_main", "fast_clk", 125, 6); + clk[enet_50m] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); + clk[enet_25m] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); + /* Video pll: default 960Mhz */ + clk[pll6_main] = imx_clk_fixed_factor("pll6_main", "fast_clk", 40, 1); + clk[pll1_sw] = imx_clk_mux("pll1_sw", CCM_CCSR, 16, 3, pll1_pfd_sel, 5); + clk[pll2_sw] = imx_clk_mux("pll2_sw", CCM_CCSR, 19, 3, pll2_pfd_sel, 5); + clk[sys_sw] = imx_clk_mux("sys_sw", CCM_CCSR, 0, 3, sys_clk_sel, ARRAY_SIZE(sys_clk_sel)); + clk[ddr_sw] = imx_clk_mux("ddr_sw", CCM_CCSR, 6, 1, ddr_clk_sel, ARRAY_SIZE(ddr_clk_sel)); + clk[sys_bus_clk] = imx_clk_divider("sys_bus", "sys_sw", CCM_CACRR, 0, 3); + clk[platform_bus_clk] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); + clk[ipg_bus_clk] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); + + clk[pll3_main_div] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); + clk[pll4_main_div] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, + CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); + clk[pll6_main_div] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); + + clk[usbc0_clk] = imx_clk_gate2("usbc0_clk", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); + clk[usbc1_clk] = imx_clk_gate2("usbc1_clk", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); + + clk[qspi0_sw] = imx_clk_mux("qspi0_sw", CCM_CSCMR1, 22, 2, qspi_clk_sel, 4); + clk[qspi0_x4_div] = imx_clk_divider("qspi0_x4", "qspi0_sw", CCM_CSCDR3, 0, 2); + clk[qspi0_x2_div] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); + clk[qspi0_x1_div] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); + clk[qspi0_gate] = imx_clk_gate("qspi0_gate", "qspi0_x1", CCM_CSCDR3, 4); + clk[qspi0_clk] = imx_clk_gate2("qspi0_clk", "qspi0_en", CCM_CCGR2, CCM_CCGRx_CGn(4)); + + clk[qspi1_sw] = imx_clk_mux("qspi1_sw", CCM_CSCMR1, 24, 2, qspi_clk_sel, 4); + clk[qspi1_x4_div] = imx_clk_divider("qspi1_x4", "qspi1_sw", CCM_CSCDR3, 8, 2); + clk[qspi1_x2_div] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); + clk[qspi1_x1_div] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); + clk[qspi1_gate] = imx_clk_gate("qspi1_gate", "qspi1_x1", CCM_CSCDR3, 12); + clk[qspi1_clk] = imx_clk_gate2("qspi1_clk", "qspi1_en", CCM_CCGR8, CCM_CCGRx_CGn(4)); + + clk[enet_clk_sw] = imx_clk_mux("enet_sw", CCM_CSCMR2, 4, 2, rmii_clk_sel, 4); + clk[enet_ts_sw] = imx_clk_mux("enet_ts_sw", CCM_CSCMR2, 0, 3, enet_ts_clk_sel, 7); + clk[enet_clk] = imx_clk_gate("enet_clk", "enet_sw", CCM_CSCDR1, 24); + clk[enet_ts] = imx_clk_gate("enet_ts_clk", "enet_ts_sw", CCM_CSCDR1, 23); + + clk[pit_clk] = imx_clk_gate2("pit_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); + + clk[uart0_clk] = imx_clk_gate2("uart0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); + clk[uart1_clk] = imx_clk_gate2("uart1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); + clk[uart2_clk] = imx_clk_gate2("uart2_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); + clk[uart3_clk] = imx_clk_gate2("uart3_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); + + clk[i2c0_clk] = imx_clk_gate2("i2c0_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); + clk[i2c1_clk] = imx_clk_gate2("i2c1_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); + + clk[dspi0_clk] = imx_clk_gate2("dspi0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); + clk[dspi1_clk] = imx_clk_gate2("dspi1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); + clk[dspi2_clk] = imx_clk_gate2("dspi2_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); + clk[dspi3_clk] = imx_clk_gate2("dspi3_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); + + clk[wdt_clk] = imx_clk_gate2("wdt_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); + + clk[esdhc0_sw] = imx_clk_mux("esdhc0_sw", CCM_CSCMR1, 16, 2, esdhc_clk_sel, 4); + clk[esdhc0_gate] = imx_clk_gate("esdhc0_gate", "esdhc0_sw", CCM_CSCDR2, 28); + clk[esdhc0_div] = imx_clk_divider("esdhc0_div", "esdhc0_gate", CCM_CSCDR2, 16, 4); + clk[esdhc0_clk] = imx_clk_gate2("eshc0_clk", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); + + clk[esdhc1_sw] = imx_clk_mux("esdhc1_sw", CCM_CSCMR1, 18, 2, esdhc_clk_sel, 4); + clk[esdhc1_gate] = imx_clk_gate("esdhc1_gate", "esdhc1_sw", CCM_CSCDR2, 29); + clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc1_gate", CCM_CSCDR2, 20, 4); + clk[esdhc1_clk] = imx_clk_gate2("eshc1_clk", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); + + /* + * ftm_ext_clk and ftm_fix_clk are FTM timer counter's + * selectable clock source, both use a common gate bit + * in CCM_CSCDR1, select "dummy" as "ftm0_ext_fix_gate" + * parent make the gate doesn't provids any clock freq + * except for gate/ungate. + */ + clk[ftm0_ext_sw] = imx_clk_mux("ftm0_ext_sw", CCM_CSCMR2, 6, 2, ftm_ext_clk_sel, 4); + clk[ftm0_fix_sw] = imx_clk_mux("ftm0_fix_sw", CCM_CSCMR2, 14, 1, ftm_fix_clk_sel, 2); + clk[ftm0_ext_fix_gate] = imx_clk_gate("ftm0_ext_fix_gate", "dummy", CCM_CSCDR1, 25); + /* ftm(n)_clk are FTM module operation clock */ + clk[ftm0_clk] = imx_clk_gate2("ftm0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); + clk[ftm1_clk] = imx_clk_gate2("ftm1_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); + clk[ftm2_clk] = imx_clk_gate2("ftm2_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); + clk[ftm3_clk] = imx_clk_gate2("ftm3_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); + + clk[dcu0_sw] = imx_clk_mux("dcu0_sw", CCM_CSCMR1, 28, 1, dcu_clk_sel, 2); + clk[dcu0_gate] = imx_clk_gate("dcu0_gate", "dcu0_sw", CCM_CSCDR3, 19); + clk[dcu0_div] = imx_clk_divider("dcu0_div", "dcu0_gate", CCM_CSCDR3, 16, 3); + clk[dcu0_clk] = imx_clk_gate2("dcu0_clk", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); + clk[dcu1_sw] = imx_clk_mux("dcu1_sw", CCM_CSCMR1, 29, 1, dcu_clk_sel, 2); + clk[dcu1_gate] = imx_clk_gate("dcu1_gate", "dcu1_sw", CCM_CSCDR3, 23); + clk[dcu1_div] = imx_clk_divider("dcu1_div", "dcu1_gate", CCM_CSCDR3, 20, 3); + clk[dcu1_clk] = imx_clk_gate2("dcu1_clk", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); + + clk[esai_sw] = imx_clk_mux("esai_sw", CCM_CSCMR1, 20, 2, esai_clk_sel, 4); + clk[esai_gate] = imx_clk_gate("esai_gate", "esai_sw", CCM_CSCDR2, 30); + clk[esai_div] = imx_clk_divider("esai_div", "esai_gate", CCM_CSCDR2, 24, 4); + clk[esai_clk] = imx_clk_gate2("esai_clk", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); + + clk[sai0_sw] = imx_clk_mux("sai0_sw", CCM_CSCMR1, 0, 2, sai_clk_sel, 4); + clk[sai0_gate] = imx_clk_gate("sai0_gate", "sai0_sw", CCM_CSCDR1, 16); + clk[sai0_div] = imx_clk_divider("sai0_div", "sai0_gate", CCM_CSCDR1, 0, 4); + clk[sai0_clk] = imx_clk_gate2("sai0_clk", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); + + clk[sai1_sw] = imx_clk_mux("sai1_sw", CCM_CSCMR1, 2, 2, sai_clk_sel, 4); + clk[sai1_gate] = imx_clk_gate("sai1_gate", "sai1_sw", CCM_CSCDR1, 17); + clk[sai1_div] = imx_clk_divider("sai1_div", "sai1_gate", CCM_CSCDR1, 4, 4); + clk[sai1_clk] = imx_clk_gate2("sai1_clk", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); + + clk[sai2_sw] = imx_clk_mux("sai2_sw", CCM_CSCMR1, 4, 2, sai_clk_sel, 4); + clk[sai2_gate] = imx_clk_gate("sai2_gate", "sai2_sw", CCM_CSCDR1, 18); + clk[sai2_div] = imx_clk_divider("sai2_div", "sai2_gate", CCM_CSCDR1, 8, 4); + clk[sai2_clk] = imx_clk_gate2("sai2_clk", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); + + clk[sai3_sw] = imx_clk_mux("sai3_sw", CCM_CSCMR1, 6, 2, sai_clk_sel, 4); + clk[sai3_gate] = imx_clk_gate("sai3_gate", "sai3_sw", CCM_CSCDR1, 19); + clk[sai3_div] = imx_clk_divider("sai3_div", "sai3_gate", CCM_CSCDR1, 12, 4); + clk[sai3_clk] = imx_clk_gate2("sai3_clk", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); + + clk[nfc_sw] = imx_clk_mux("nfc_sw", CCM_CSCMR1, 12, 2, nfc_clk_sel, 4); + clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_sw", CCM_CSCDR2, 9); + clk[nfc_pre_div] = imx_clk_divider("nfc_pre_div", "nfc_gate", CCM_CSCDR3, 13, 3); + clk[nfc_frac_div] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); + clk[nfc_clk] = imx_clk_gate2("nfc_clk", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); + + clk[gpu_sw] = imx_clk_mux("gpu_sw", CCM_CSCMR1, 14, 1, gpu_clk_sel, 2); + clk[gpu_gate] = imx_clk_gate("gpu_gate", "gpu_sw", CCM_CSCDR2, 10); + clk[gpu2d_clk] = imx_clk_gate2("gpu_clk", "gpu_gate", CCM_CCGR8, CCM_CCGRx_CGn(15)); + + clk[vadc_sw] = imx_clk_mux("vadc_sw", CCM_CSCMR1, 8, 2, vadc_clk_sel, 3); + clk[vadc_gate] = imx_clk_gate("vadc_gate", "vadc_sw", CCM_CSCDR1, 22); + clk[vadc_div] = imx_clk_divider("vadc_div", "vadc_gate", CCM_CSCDR1, 20, 2); + clk[vadc_div_half] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); + clk[vadc_clk] = imx_clk_gate2("vadc_clk", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); + + clk[adc0_clk] = imx_clk_gate2("adc0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); + clk[adc1_clk] = imx_clk_gate2("adc1_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); + clk[dac0_clk] = imx_clk_gate2("dac0_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); + clk[dac1_clk] = imx_clk_gate2("dac1_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); + + clk[asrc_clk] = imx_clk_gate2("asrc_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); + + clk[flexcan0_clk] = imx_clk_gate2("flexcan0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); + clk[flexcan1_clk] = imx_clk_gate2("flexcan1_clk", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + + clk_set_parent(clk[qspi0_sw], clk[pll1_pfd4_528m]); + clk_set_rate(clk[qspi0_x4_div], clk_get_rate(clk[qspi0_x4_div]->parent) / 2); + clk_set_rate(clk[qspi0_x2_div], clk_get_rate(clk[qspi0_x2_div]->parent) / 2); + clk_set_rate(clk[qspi0_x1_div], clk_get_rate(clk[qspi0_x1_div]->parent) / 2); + + clk_set_parent(clk[qspi1_sw], clk[pll1_pfd4_528m]); + clk_set_rate(clk[qspi1_x4_div], clk_get_rate(clk[qspi1_x4_div]->parent) / 2); + clk_set_rate(clk[qspi1_x2_div], clk_get_rate(clk[qspi1_x2_div]->parent) / 2); + clk_set_rate(clk[qspi1_x1_div], clk_get_rate(clk[qspi1_x1_div]->parent) / 2); + + clk_set_parent(clk[sai0_gate], clk[audio_ext]); + clk_set_parent(clk[sai1_gate], clk[audio_ext]); + clk_set_parent(clk[sai2_gate], clk[audio_ext]); + clk_set_parent(clk[sai3_gate], clk[audio_ext]); + + /* Add the clocks to provider list */ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + return 0; +} diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 4cba7db..683c4f4 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -68,6 +68,7 @@ extern int mx31_clocks_init_dt(void); extern int mx51_clocks_init_dt(void); extern int mx53_clocks_init_dt(void); extern int mx6q_clocks_init(void); +extern int mvf_clocks_init(void); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c new file mode 100644 index 0000000..56d3fb0 --- /dev/null +++ b/arch/arm/mach-imx/mach-mvf600.c @@ -0,0 +1,118 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clocksource.h> +#include <linux/platform_device.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> +#include <asm/memory.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/system_misc.h> + +#include "common.h" + + +void mvf_restart(char mode, const char *cmd) +{ + struct device_node *np; + void __iomem *wdog_base; + struct clk *wdog_clk; + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt"); + wdog_base = of_iomap(np, 0); + if (!wdog_base) + goto soft; + + wdog_clk = of_clk_get_by_name(np, "wdog"); + if (!IS_ERR(wdog_clk)) + clk_prepare_enable(wdog_clk); + + /* enable wdog */ + writew_relaxed(1 << 2, wdog_base); + + /* wait for reset to assert ... */ + mdelay(500); + + pr_err("Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + +soft: + /* we'll take a jump through zero as a poor second */ + soft_restart(0); +} + +static void __init mvf_init_machine(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init mvf_of_init_irq(void) +{ + struct device_node *np; + void __iomem *mscm_base; + int i; + + l2x0_of_init(0, ~0UL); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-mscm"); + mscm_base = of_iomap(np, 0); + if (!mscm_base) + return; + + /* route each shared peripheral interrupt to CP0 */ + for (i = 0; i < 111; i++) + __raw_writew(1, mscm_base + 0x880 + 2 * i); + + iounmap(mscm_base); + + irqchip_init(); +} + +static void __init mvf_timer_init(void) +{ + mvf_clocks_init(); + clocksource_of_init(); +} + +/* + * initialize __mach_desc_ data structure. + */ +static const char *mvf_dt_compat[] __initdata = { + "fsl,mvf600", + NULL, +}; + +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid Family (Device Tree)") + .init_irq = mvf_of_init_irq, + .init_machine = mvf_init_machine, + .init_time = mvf_timer_init, + .dt_compat = mvf_dt_compat, + .restart = mvf_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/pit.c b/arch/arm/mach-imx/pit.c new file mode 100644 index 0000000..e2df0e5 --- /dev/null +++ b/arch/arm/mach-imx/pit.c @@ -0,0 +1,244 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <asm/mach/time.h> +#include <asm/sched_clock.h> + + +#define PITMCR 0x00 +#define PITLTMR64H 0xE0 +#define PITLTMR64L 0xE4 + +#define PITLDVAL 0x00 +#define PITCVAL 0x04 +#define PITTCTRL 0x08 +#define PITTFLG 0x0C + +/* + * Vybrid has 8 pit timers: pit0 - pit7, + * Each memory mapped register occupy 0x10 Bytes + */ +#define PITOFFSET0 0x100 +#define PITOFFSETx(n) (PITOFFSET0 + 0x10 * n) + +/* bit definitation */ +#define PITMCR_MDIS (1 << 1) +#define PITMCR_FRZ (1 << 0) + +#define PITTCTRL_TEN (1 << 0) +#define PITTCTRL_TIE (1 << 1) +#define PITCTRL_CHN (1 << 2) + +#define PITTFLG_TIF 0x1 + +static struct clock_event_device clockevent_pit; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *clksrc_base; +static void __iomem *clkevt_base; +static void __iomem *sched_clock_reg; +static unsigned long pit_cycle_per_jiffy; + +static inline void pit_timer_enable(void) +{ + __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); +} + +static inline void pit_timer_disable(void) +{ + __raw_writel(0, clkevt_base + PITTCTRL); +} + +static inline void pit_irq_disable(void) +{ + unsigned long val; + + val = __raw_readl(clkevt_base + PITTCTRL); + val &= ~PITTCTRL_TIE; + __raw_writel(val, clkevt_base + PITTCTRL); +} + +static inline void pit_irq_enable(void) +{ + unsigned long val; + + val = __raw_readl(clkevt_base + PITTCTRL); + val |= PITTCTRL_TIE; + __raw_writel(val, clkevt_base + PITTCTRL); +} + +static void pit_irq_acknowledge(void) +{ + __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); +} + +static unsigned int mvf_read_sched_clock(void) +{ + return __raw_readl(sched_clock_reg); +} + + +static int __init pit_clocksource_init(struct clk *pit_clk) +{ + unsigned int c = clk_get_rate(pit_clk); + + sched_clock_reg = clksrc_base + PITCVAL; + + setup_sched_clock(mvf_read_sched_clock, 32, c); + return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32, + clocksource_mmio_readl_down); +} + +/* set clock event */ +static int pit_set_next_event(unsigned long delta, + struct clock_event_device *unused) +{ + pit_timer_disable(); + __raw_writel(delta - 1, clkevt_base + PITLDVAL); + pit_irq_acknowledge(); + pit_timer_enable(); + + return 0; +} + +static void pit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + local_irq_save(flags); + + pit_timer_disable(); + pit_irq_acknowledge(); + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + + __raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL); + pit_timer_enable(); + + break; + case CLOCK_EVT_MODE_ONESHOT: + + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + + break; + default: + WARN(1, "%s: unhandled event mode %d\n", __func__, mode); + break; + } +} + +/* + * interrupt handler for the timer + */ +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_pit; + + pit_irq_acknowledge(); + + if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT) + pit_timer_disable(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction pit_timer_irq = { + .name = "MVF PIT Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = pit_timer_interrupt, +}; + +static struct clock_event_device clockevent_pit = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = pit_set_mode, + .set_next_event = pit_set_next_event, + .rating = 300, +}; + +static int __init pit_clockevent_init(struct clk *pit_clk) +{ + unsigned int c = clk_get_rate(pit_clk); + + clockevent_pit.cpumask = cpumask_of(0); + clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00); + + return 0; +} + +static void __init pit_timer_init(struct device_node *np) +{ + struct clk *pit_clk; + void __iomem *timer_base; + int irq; + + if (!np) { + pr_err("Failed to find pit DT node\n"); + BUG(); + } + + timer_base = of_iomap(np, 0); + WARN_ON(!timer_base); + + /* chose PIT2 as clocksource, PIT3 as clockevent dev */ + clksrc_base = timer_base + PITOFFSETx(2); + clkevt_base = timer_base + PITOFFSETx(3); + + irq = irq_of_parse_and_map(np, 0); + + pit_clk = of_clk_get_by_name(np, "pit"); + if (IS_ERR(pit_clk)) { + pr_err("Vybrid PIT timer: unable to get clk\n"); + return; + } + + clk_prepare_enable(pit_clk); + + pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ); + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + __raw_writel(0x0, timer_base + PITMCR); + + __raw_writel(0, clkevt_base + PITTCTRL); + __raw_writel(0xffffffff, clkevt_base + PITLDVAL); + + __raw_writel(0, clksrc_base + PITTCTRL); + __raw_writel(0xffffffff, clksrc_base + PITLDVAL); + __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); + + pit_clocksource_init(pit_clk); + + setup_irq(irq, &pit_timer_irq); + + pit_clockevent_init(pit_clk); +} + +CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf-pit", pit_timer_init); -- 1.8.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu @ 2013-05-02 8:52 ` Sascha Hauer 2013-05-02 9:20 ` Lu Jingchang-B35083 2013-05-02 16:53 ` Mike Turquette ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Sascha Hauer @ 2013-05-02 8:52 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote: > This patch adds Freescale Vybrid Family platform core definitions, > core drivers, including clock, period interrupt timer(PIT), > and DTS based machine support with MVF600 Tower development board. > > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > V2: > Use CLOCKSOURCE_OF_DECLARE init timer > Add ONESHOT mode support > Add more clks definitions on MVF600 soc > > .../devicetree/bindings/clock/mvf600-clock.txt | 180 +++++++++ > arch/arm/mach-imx/Kconfig | 15 + > arch/arm/mach-imx/Makefile | 3 + > arch/arm/mach-imx/clk-mvf.c | 406 +++++++++++++++++++++ > arch/arm/mach-imx/common.h | 1 + > arch/arm/mach-imx/mach-mvf600.c | 118 ++++++ > arch/arm/mach-imx/pit.c | 244 +++++++++++++ > 7 files changed, 967 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt > create mode 100644 arch/arm/mach-imx/clk-mvf.c > create mode 100644 arch/arm/mach-imx/mach-mvf600.c > create mode 100644 arch/arm/mach-imx/pit.c > > diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt > new file mode 100644 > index 0000000..9f8b20e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt [...] > + sys_bus_clk 36 > + platform_bus_clk 37 > + ipg_bus_clk 38 > + uart0_clk 39 > + uart1_clk 40 > + uart2_clk 41 > + uart3_clk 42 > + uart4_clk 43 > + uart5_clk 44 remove the _clk. The context makes it clear that it's a clock. > + > +#define CCM_CCGRx_CGn(n) (n * 2) Does CCM_CCGRx_CGn(1 + 1) give correct results? Always add braces to the usage of macro arguments. > +int __init mvf_clocks_init(void) > +{ > + struct device_node *np; > + > + clk[dummy] = imx_clk_fixed("dummy", 0); > + clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */ > + clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */ > + clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */ > + clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */ > + > + for_each_compatible_node(np, NULL, "fixed-clock") { > + u32 rate; > + > + if (of_property_read_u32(np, "clock-frequency", &rate)) > + continue; > + else if (of_device_is_compatible(np, "fsl,mvf-osc")) > + clk[fxosc] = imx_clk_fixed("fxosc", rate); > + else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk")) > + clk[audio_ext] = imx_clk_fixed("audio_ext", rate); > + else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk")) > + clk[enet_ext] = imx_clk_fixed("enet_ext", rate); > + } Please do the same as https://patchwork.kernel.org/patch/2476681/ does for i.MX5. > + > + > +void mvf_restart(char mode, const char *cmd) > +{ > + struct device_node *np; > + void __iomem *wdog_base; > + struct clk *wdog_clk; > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt"); > + wdog_base = of_iomap(np, 0); > + if (!wdog_base) > + goto soft; > + > + wdog_clk = of_clk_get_by_name(np, "wdog"); use of_clk_get. > + > + > +static int __init pit_clocksource_init(struct clk *pit_clk) > +{ > + unsigned int c = clk_get_rate(pit_clk); > + > + sched_clock_reg = clksrc_base + PITCVAL; > + > + setup_sched_clock(mvf_read_sched_clock, 32, c); > + return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32, > + clocksource_mmio_readl_down); > +} > + > +/* set clock event */ > +static int pit_set_next_event(unsigned long delta, > + struct clock_event_device *unused) > +{ > + pit_timer_disable(); > + __raw_writel(delta - 1, clkevt_base + PITLDVAL); > + pit_irq_acknowledge(); > + pit_timer_enable(); You disable/enable the timer each time here, is this necessary? You will get a drift in the timer, that's really not nice. > + > +static void __init pit_timer_init(struct device_node *np) > +{ > + struct clk *pit_clk; > + void __iomem *timer_base; > + int irq; > + > + if (!np) { > + pr_err("Failed to find pit DT node\n"); > + BUG(); > + } > + > + timer_base = of_iomap(np, 0); > + WARN_ON(!timer_base); > + > + /* chose PIT2 as clocksource, PIT3 as clockevent dev */ > + clksrc_base = timer_base + PITOFFSETx(2); > + clkevt_base = timer_base + PITOFFSETx(3); > + > + irq = irq_of_parse_and_map(np, 0); > + > + pit_clk = of_clk_get_by_name(np, "pit"); Use of_clk_get Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 8:52 ` Sascha Hauer @ 2013-05-02 9:20 ` Lu Jingchang-B35083 0 siblings, 0 replies; 13+ messages in thread From: Lu Jingchang-B35083 @ 2013-05-02 9:20 UTC (permalink / raw) To: linux-arm-kernel >-----Original Message----- >From: Sascha Hauer [mailto:s.hauer at pengutronix.de] >Sent: Thursday, May 02, 2013 4:53 PM >To: Lu Jingchang-B35083 >Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org >Subject: Re: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support > >> +static int __init pit_clocksource_init(struct clk *pit_clk) { >> + unsigned int c = clk_get_rate(pit_clk); >> + >> + sched_clock_reg = clksrc_base + PITCVAL; >> + >> + setup_sched_clock(mvf_read_sched_clock, 32, c); >> + return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, >32, >> + clocksource_mmio_readl_down); >> +} >> + >> +/* set clock event */ >> +static int pit_set_next_event(unsigned long delta, >> + struct clock_event_device *unused) { >> + pit_timer_disable(); >> + __raw_writel(delta - 1, clkevt_base + PITLDVAL); >> + pit_irq_acknowledge(); >> + pit_timer_enable(); > >You disable/enable the timer each time here, is this necessary? You will >get a drift in the timer, that's really not nice. > [Lu Jingchang-B35083] Disable/enable the timer each time is due to the pit hardware mechanism: Writing a new value to PIT_LDVAL register will not restart the timer; instead the value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again. It won't affect the clocksoure timer which runs continuously and separately. Thanks! Best Regards, Jingchang Lu ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu 2013-05-02 8:52 ` Sascha Hauer @ 2013-05-02 16:53 ` Mike Turquette 2013-05-03 7:41 ` Shawn Guo 2013-05-08 18:03 ` Russell King - ARM Linux 3 siblings, 0 replies; 13+ messages in thread From: Mike Turquette @ 2013-05-02 16:53 UTC (permalink / raw) To: linux-arm-kernel Quoting Jingchang Lu (2013-05-02 00:38:04) > diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c > new file mode 100644 > index 0000000..1467a304 > --- /dev/null > +++ b/arch/arm/mach-imx/clk-mvf.c > @@ -0,0 +1,406 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + */ > + > +#include <linux/kernel.h> > +#include <linux/init.h> > +#include <linux/types.h> > +#include <linux/time.h> > +#include <linux/hrtimer.h> > +#include <linux/mm.h> > +#include <linux/errno.h> > +#include <linux/delay.h> > +#include <linux/clk.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/ioport.h> > +#include <linux/clkdev.h> > +#include <linux/regulator/consumer.h> > +#include <asm/div64.h> > +#include <linux/clk-provider.h> > +#include <linux/clk-private.h> Please do not use clk-private.h. I plan to remove it soon. Regards, Mike ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu 2013-05-02 8:52 ` Sascha Hauer 2013-05-02 16:53 ` Mike Turquette @ 2013-05-03 7:41 ` Shawn Guo 2013-05-08 7:26 ` Lu Jingchang-B35083 2013-05-08 18:03 ` Russell King - ARM Linux 3 siblings, 1 reply; 13+ messages in thread From: Shawn Guo @ 2013-05-03 7:41 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote: > This patch adds Freescale Vybrid Family platform core definitions, > core drivers, including clock, period interrupt timer(PIT), IMO, separating the patch into 3 would make the reviewing and merging a little easier, e.g. one patch for PIT, one patch for clock driver, and one for the rest. And this is what I have done for i.MX6 SoloLite series which I have copied you on. > and DTS based machine support with MVF600 Tower development board. You do not have these in this patch. > > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > V2: > Use CLOCKSOURCE_OF_DECLARE init timer > Add ONESHOT mode support > Add more clks definitions on MVF600 soc > > .../devicetree/bindings/clock/mvf600-clock.txt | 180 +++++++++ > arch/arm/mach-imx/Kconfig | 15 + > arch/arm/mach-imx/Makefile | 3 + > arch/arm/mach-imx/clk-mvf.c | 406 +++++++++++++++++++++ If the bindings doc is named mvf600-clock, the clock driver should probably be named clk-mvf600.c? > arch/arm/mach-imx/common.h | 1 + > arch/arm/mach-imx/mach-mvf600.c | 118 ++++++ > arch/arm/mach-imx/pit.c | 244 +++++++++++++ We're recently moving ARM timer drivers into drivers/clocksource. I think PIT should probably be done that way from the beginning. > 7 files changed, 967 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt > create mode 100644 arch/arm/mach-imx/clk-mvf.c > create mode 100644 arch/arm/mach-imx/mach-mvf600.c > create mode 100644 arch/arm/mach-imx/pit.c > > diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt > new file mode 100644 > index 0000000..9f8b20e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt > @@ -0,0 +1,180 @@ > +* Clock bindings for Freescale Vybrid Family The file name suggest this is a bindings for SoC mvf600, but subject tells it's for Vybrid Family. I think these are two slightly different things, and mvf600 is only a member of Vybrid Family. > + > +Required properties: > +- compatible: Should be "fsl,mvf-ccm" If this is a compatible of given SoC, it should be "fsl,mvf600-ccm"? > +- reg: Address and length of the register set > +- interrupts: Should contain CCM interrupt I know this is copied from IMX, but if you have no interrupt for CCM, you shouldn't list it as a required property. I do not see you define the property for "ccm" node in the example below. > +- #clock-cells: Should be <1> > + > +The clock consumer should specify the desired clock by having the clock > +ID in its "clocks" phandle cell. The following is a full list of MVF600 > +clocks and IDs. > + > + Clock ID In the imx6sl clock patch I copied you, we choose to use DTC macro support to define these clock IDs as macro in a header, and have both kernel and DTS include the header. Doing so will help maintain the data consistency between kernel and DT. > + --------------------------- > + dummy 0 > + sirc_128k 1 > + sirc_32k 2 > + firc 3 > + sxosc 4 > + fxosc 5 > + fxosc_half 6 > + slow_clk 7 > + fast_clk 8 > + audio_ext 9 > + enet_ext 10 > + pll1_main_528m 11 > + pll1_pfd1_500m 12 > + pll1_pfd2_452m 13 > + pll1_pfd3_396m 14 > + pll1_pfd4_528m 15 > + pll2_main_528m 16 > + pll2_pfd1_500m 17 > + pll2_pfd2_396m 18 > + pll2_pfd3_339m 19 > + pll2_pfd4_413m 20 > + pll3_main_480m 21 > + pll3_pfd1_308m 22 > + pll3_pfd2_332m 23 > + pll3_pfd3_298m 24 > + pll3_pfd4_320m 25 > + pll4_main 26 > + pll5_main 27 > + pll6_main 28 > + pll3_main_div 29 > + pll4_main_div 30 > + pll6_main_div 31 > + pll1_sw 32 > + pll2_sw 33 > + sys_sw 34 > + ddr_sw 35 > + sys_bus_clk 36 > + platform_bus_clk 37 > + ipg_bus_clk 38 > + uart0_clk 39 > + uart1_clk 40 > + uart2_clk 41 > + uart3_clk 42 > + uart4_clk 43 > + uart5_clk 44 > + pit_clk 45 > + i2c0_clk 46 > + i2c1_clk 47 > + i2c2_clk 48 > + i2c3_clk 49 > + ftm0_ext_sw 50 > + ftm0_fix_sw 51 > + ftm0_ext_fix_gate 52 > + ftm1_ext_sw 53 > + ftm1_fix_sw 54 > + ftm1_ext_fix_gate 55 > + ftm2_ext_sw 56 > + ftm2_fix_sw 57 > + ftm2_ext_fix_gate 58 > + ftm3_ext_sw 59 > + ftm3_fix_sw 60 > + ftm3_ext_fix_gate 61 > + ftm0_clk 62 > + ftm1_clk 63 > + ftm2_clk 64 > + ftm3_clk 65 > + enet_50m 66 > + enet_25m 67 > + enet_clk_sw 68 > + enet_clk 69 > + enet_ts_sw 70 > + enet_ts 71 > + dspi0_clk 72 > + dspi1_clk 73 > + dspi2_clk 74 > + dspi3_clk 75 > + wdt_clk 76 > + esdhc0_sw 77 > + esdhc0_gate 78 > + esdhc0_div 79 > + esdhc0_clk 80 > + esdhc1_sw 81 > + esdhc1_gate 82 > + esdhc1_div 83 > + esdhc1_clk 84 > + dcu0_sw 85 > + dcu0_gate 86 > + dcu0_div 87 > + dcu0_clk 88 > + dcu1_sw 89 > + dcu1_gate 90 > + dcu1_div 91 > + dcu1_clk 92 > + esai_sw 93 > + esai_gate 94 > + esai_div 95 > + esai_clk 96 > + sai0_sw 97 > + sai0_gate 98 > + sai0_div 99 > + sai0_clk 100 > + sai1_sw 101 > + sai1_gate 102 > + sai1_div 103 > + sai1_clk 104 > + sai2_sw 105 > + sai2_gate 106 > + sai2_div 107 > + sai2_clk 108 > + sai3_sw 109 > + sai3_gate 110 > + sai3_div 111 > + sai3_clk 112 > + usbc0_clk 113 > + usbc1_clk 114 > + qspi0_sw 115 > + qspi0_gate 116 > + qspi0_x4_div 117 > + qspi0_x2_div 118 > + qspi0_x1_div 119 > + qspi1_sw 120 > + qspi1_gate 121 > + qspi1_x4_div 122 > + qspi1_x2_div 123 > + qspi1_x1_div 124 > + qspi0_clk 125 > + qspi1_clk 126 > + nfc_sw 127 > + nfc_gate 128 > + nfc_pre_div 129 > + nfc_frac_div 130 > + nfc_inv 131 > + nfc_clk 132 > + vadc_sw 133 > + vadc_gate 134 > + vadc_div 135 > + vadc_div_half 136 > + vadc_clk 137 > + adc0_clk 138 > + adc1_clk 139 > + dac0_clk 140 > + dac1_clk 141 > + flexcan0_clk 142 > + flexcan1_clk 143 > + asrc_clk 144 > + gpu_sw 145 > + gpu_gate 146 > + gpu2d_clk 147 > + > + > + > +Examples: > + > +clks: ccm at 4006b000 { > + compatible = "fsl,mvf-ccm"; > + reg = <0x4006b000 0x1000>; > + #clock-cells = <1>; > +}; > + > +uart1: serial at 40028000 { /* UART1 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x40028000 0x1000>; > + interrupts = <0 62 0x04>; > + clocks = <&clks 35>; > + clock-names = "ipg"; > +}; > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig > index 78f795d..2fb9562 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -819,6 +819,21 @@ config SOC_IMX6Q > help > This enables support for Freescale i.MX6 Quad processor. > > +config SOC_MVF600 > + bool "Vybrid Family MVF600 support" > + select CPU_V7 > + select ARM_GIC > + select COMMON_CLK This one has been select by ARCH_MULTIPLATFORM. As IMX/MXC is part of multiplatform build now, this select of COMMON_CLK is redundant. > + select CLKSRC_OF > + select PINCTRL > + select PINCTRL_MVF > + select PL310_ERRATA_588369 if CACHE_PL310 > + select PL310_ERRATA_727915 if CACHE_PL310 > + select PL310_ERRATA_769419 if CACHE_PL310 > + > + help > + This enable support for Freescale Vybrid Family VF6xx MPU. > + > endif > > source "arch/arm/mach-imx/devices/Kconfig" > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index b16eb39..76a2ead 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -112,4 +112,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o > obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o > obj-$(CONFIG_SOC_IMX53) += mach-imx53.o > > +# Vybrid based machines The comment is a little confusing, as "machines" means the board files which have been replaced by device tree support. The comment is not so helpful anyway, so please just remove it. > +obj-$(CONFIG_SOC_MVF600) += clk-mvf.o mach-mvf600.o pit.o > + > obj-y += devices/ > diff --git a/arch/arm/mach-imx/clk-mvf.c b/arch/arm/mach-imx/clk-mvf.c > new file mode 100644 > index 0000000..1467a304 > --- /dev/null > +++ b/arch/arm/mach-imx/clk-mvf.c > @@ -0,0 +1,406 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + */ > + > +#include <linux/kernel.h> > +#include <linux/init.h> > +#include <linux/types.h> > +#include <linux/time.h> > +#include <linux/hrtimer.h> > +#include <linux/mm.h> > +#include <linux/errno.h> > +#include <linux/delay.h> > +#include <linux/clk.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/ioport.h> > +#include <linux/clkdev.h> Do you need this header? > +#include <linux/regulator/consumer.h> Ditto > +#include <asm/div64.h> Ditto > +#include <linux/clk-provider.h> > +#include <linux/clk-private.h> Ditto > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> Ditto > + > +#include "hardware.h" And this? You should only include the headers that you really need. > +#include "common.h" > +#include "clk.h" > + > + One blank line is enough. > +#define CCM_CCR (ccm_base + 0x00) > +#define CCM_CSR (ccm_base + 0x04) > +#define CCM_CCSR (ccm_base + 0x08) > +#define CCM_CACRR (ccm_base + 0x0c) > +#define CCM_CSCMR1 (ccm_base + 0x10) > +#define CCM_CSCDR1 (ccm_base + 0x14) > +#define CCM_CSCDR2 (ccm_base + 0x18) > +#define CCM_CSCDR3 (ccm_base + 0x1c) > +#define CCM_CSCMR2 (ccm_base + 0x20) > +#define CCM_CSCDR4 (ccm_base + 0x24) > +#define CCM_CLPCR (ccm_base + 0x2c) > +#define CCM_CISR (ccm_base + 0x30) > +#define CCM_CIMR (ccm_base + 0x34) > +#define CCM_CGPR (ccm_base + 0x3c) > +#define CCM_CCGR0 (ccm_base + 0x40) > +#define CCM_CCGR1 (ccm_base + 0x44) > +#define CCM_CCGR2 (ccm_base + 0x48) > +#define CCM_CCGR3 (ccm_base + 0x4c) > +#define CCM_CCGR4 (ccm_base + 0x50) > +#define CCM_CCGR5 (ccm_base + 0x54) > +#define CCM_CCGR6 (ccm_base + 0x58) > +#define CCM_CCGR7 (ccm_base + 0x5c) > +#define CCM_CCGR8 (ccm_base + 0x60) > +#define CCM_CCGR9 (ccm_base + 0x64) > +#define CCM_CCGR10 (ccm_base + 0x68) > +#define CCM_CCGR11 (ccm_base + 0x6C) So I have seen both lowercase and uppercase in hex value. Please be consistent. My personal taste is to use lowercase. > +#define CCM_CMEOR0 (ccm_base + 0x70) > +#define CCM_CMEOR1 (ccm_base + 0x74) > +#define CCM_CMEOR2 (ccm_base + 0x78) > +#define CCM_CMEOR3 (ccm_base + 0x7C) > +#define CCM_CMEOR4 (ccm_base + 0x80) > +#define CCM_CMEOR5 (ccm_base + 0x84) > +#define CCM_CPPDSR (ccm_base + 0x88) > +#define CCM_CCOWR (ccm_base + 0x8C) > +#define CCM_CCPGR0 (ccm_base + 0x90) > +#define CCM_CCPGR1 (ccm_base + 0x94) > +#define CCM_CCPGR2 (ccm_base + 0x98) > +#define CCM_CCPGR3 (ccm_base + 0x9C) > + > +#define CCM_CCGRx_CGn(n) (n * 2) > + > +#define PFD_528SYS_BASE (anatop_base + 0x2B0) > +#define PFD_528_BASE (anatop_base + 0x100) > +#define PFD_USB_BASE (anatop_base + 0xF0) /* pll3 pfd definition */ > + > + One blank line is enough. > +static void __iomem *anatop_base; > +static void __iomem *ccm_base; > + > +/* This is used multiple times */ > +static const char const *fast_clk_sel[] = { "firc", "fxosc", }; > +static const char const *slow_clk_sel[] = { "sirc_32k", "sxosc", }; > +static const char const *pll1_pfd_sel[] = { > + "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", > +}; > +static const char const *pll2_pfd_sel[] = { > + "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", > +}; > +static const char const *sys_clk_sel[] = { > + "fast_clk", "slow_clk", "pll2_sw", "pll2_main", "pll1_sw", "pll3_main", > +}; > +static const char const *ddr_clk_sel[] = { "pll2_pfd2", "sys_clk", }; > +static const char const *rmii_clk_sel[] = { > + "enet_ext", "audio_ext", "enet_50m", "enet_25m", > +}; > +static const char const *enet_ts_clk_sel[] = { > + "enet_ext", "fxosc", "audio_ext", "usb_clk", "enet_ts_clk", "enet_25m", "enet_50m", > +}; > +static const char const *esai_clk_sel[] = { > + "audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div", > +}; > +static const char const *sai_clk_sel[] = { > + "audio_ext", "mlb_clk", "spdif_rx_clk", "pll4_main_div", > +}; > +static const char const *nfc_clk_sel[] = { > + "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", > +}; > +static const char const *qspi_clk_sel[] = { > + "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", > +}; > +static const char const *esdhc_clk_sel[] = { > + "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", > +}; > +static const char const *dcu_clk_sel[] = { "pll1_pfd2", "pll3_main", }; > +static const char const *gpu_clk_sel[] = { "pll2_pfd2", "pll3_pfd2", }; > +static const char const *vadc_clk_sel[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; > +/* FTM counter clock source, not module clock */ > +static const char const *ftm_ext_clk_sel[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; > +static const char const *ftm_fix_clk_sel[] = { "sxosc", "ipg_bus", }; > + > +enum mvf_clks { > + dummy, > + sirc_128k, sirc_32k, firc, sxosc, fxosc, fxosc_half, > + slow_clk, fast_clk, audio_ext, enet_ext, > + pll1_main_528m, pll1_pfd1_500m, pll1_pfd2_452m, > + pll1_pfd3_396m, pll1_pfd4_528m, pll2_main_528m, pll2_pfd1_500m, > + pll2_pfd2_396m, pll2_pfd3_339m, pll2_pfd4_413m, pll3_main_480m, > + pll3_pfd1_308m, pll3_pfd2_332m, pll3_pfd3_298m, pll3_pfd4_320m, > + pll4_main, pll5_main, pll6_main, > + pll3_main_div, pll4_main_div, pll6_main_div, > + pll1_sw, pll2_sw, sys_sw, ddr_sw, > + sys_bus_clk, platform_bus_clk, ipg_bus_clk, > + uart0_clk, uart1_clk, uart2_clk, uart3_clk, uart4_clk, uart5_clk, > + pit_clk, > + i2c0_clk, i2c1_clk, i2c2_clk, i2c3_clk, > + ftm0_ext_sw, ftm0_fix_sw, ftm0_ext_fix_gate, > + ftm1_ext_sw, ftm1_fix_sw, ftm1_ext_fix_gate, > + ftm2_ext_sw, ftm2_fix_sw, ftm2_ext_fix_gate, > + ftm3_ext_sw, ftm3_fix_sw, ftm3_ext_fix_gate, > + ftm0_clk, ftm1_clk, ftm2_clk, ftm3_clk, > + enet_50m, enet_25m, enet_clk_sw, enet_clk, enet_ts_sw, enet_ts, > + dspi0_clk, dspi1_clk, dspi2_clk, dspi3_clk, > + wdt_clk, > + esdhc0_sw, esdhc0_gate, esdhc0_div, esdhc0_clk, > + esdhc1_sw, esdhc1_gate, esdhc1_div, esdhc1_clk, > + dcu0_sw, dcu0_gate, dcu0_div, dcu0_clk, > + dcu1_sw, dcu1_gate, dcu1_div, dcu1_clk, > + esai_sw, esai_gate, esai_div, esai_clk, > + sai0_sw, sai0_gate, sai0_div, sai0_clk, > + sai1_sw, sai1_gate, sai1_div, sai1_clk, > + sai2_sw, sai2_gate, sai2_div, sai2_clk, > + sai3_sw, sai3_gate, sai3_div, sai3_clk, > + usbc0_clk, usbc1_clk, > + qspi0_sw, qspi0_gate, qspi0_x4_div, qspi0_x2_div, qspi0_x1_div, > + qspi1_sw, qspi1_gate, qspi1_x4_div, qspi1_x2_div, qspi1_x1_div, > + qspi0_clk, qspi1_clk, > + nfc_sw, nfc_gate, nfc_pre_div, nfc_frac_div, nfc_inv, nfc_clk, > + vadc_sw, vadc_gate, vadc_div, vadc_div_half, vadc_clk, > + adc0_clk, adc1_clk, dac0_clk, dac1_clk, > + flexcan0_clk, flexcan1_clk, > + asrc_clk, > + gpu_sw, gpu_gate, gpu2d_clk, > + clk_max > +}; > + > +static struct clk_div_table pll4_main_div_table[] = { > + [0] = {.val = 0, .div = 1}, > + [1] = {.val = 1, .div = 2}, > + [2] = {.val = 2, .div = 6}, > + [3] = {.val = 3, .div = 8}, > + [4] = {.val = 4, .div = 10}, > + [5] = {.val = 5, .div = 12}, > + [6] = {.val = 6, .div = 14}, > + [7] = {.val = 7, .div = 16}, Per kernel doc of function clk_register_divider_table(), the clk_div_table should end with a div set to 0. > +}; > +static struct clk *clk[clk_max]; > +static struct clk_onecell_data clk_data; > + > +int __init mvf_clocks_init(void) > +{ > + struct device_node *np; > + > + clk[dummy] = imx_clk_fixed("dummy", 0); > + clk[sirc_128k] = imx_clk_fixed("sirc_128k", 128000); /* slow internal IRC */ > + clk[sirc_32k] = imx_clk_fixed("sirc_32k", 32000); /* slow internal IRC */ > + clk[firc] = imx_clk_fixed("firc", 24000000); /* fast internal IRC */ > + clk[sxosc] = imx_clk_fixed("sxosc", 32000); /* fixed 32k external osc */ > + > + for_each_compatible_node(np, NULL, "fixed-clock") { > + u32 rate; > + > + if (of_property_read_u32(np, "clock-frequency", &rate)) > + continue; > + else if (of_device_is_compatible(np, "fsl,mvf-osc")) > + clk[fxosc] = imx_clk_fixed("fxosc", rate); > + else if (of_device_is_compatible(np, "fsl,mvf-audio-ext-clk")) > + clk[audio_ext] = imx_clk_fixed("audio_ext", rate); > + else if (of_device_is_compatible(np, "fsl,mvf-enet-ext-clk")) > + clk[enet_ext] = imx_clk_fixed("enet_ext", rate); > + } > + > + /* default to 24Mhz OSC */ > + if (!clk[fxosc]) > + clk[fxosc] = imx_clk_fixed("fxosc", 24000000); > + > + clk[fxosc_half] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-anatop"); > + anatop_base = of_iomap(np, 0); > + WARN_ON(!anatop_base); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-ccm"); > + ccm_base = of_iomap(np, 0); > + WARN_ON(!ccm_base); > + > + clk[slow_clk] = imx_clk_mux("slow_clk", CCM_CCSR, 4, 1, > + slow_clk_sel, ARRAY_SIZE(slow_clk_sel)); I would suggest we name the clocks as close as how reference manual names them. For above example, it would be: clk[slow_clk_sel] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_clk_sels, ARRAY_SIZE(slow_clk_sels)); > + clk[fast_clk] = imx_clk_mux("fast_clk", CCM_CCSR, 5, 1, > + fast_clk_sel, ARRAY_SIZE(fast_clk_sel)); > + > + clk[pll1_main_528m] = imx_clk_fixed_factor("pll1_main", "fast_clk", 22, 1); > + clk[pll1_pfd1_500m] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_528SYS_BASE, 0); > + clk[pll1_pfd2_452m] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_528SYS_BASE, 1); > + clk[pll1_pfd3_396m] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_528SYS_BASE, 2); > + clk[pll1_pfd4_528m] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_528SYS_BASE, 3); > + > + clk[pll2_main_528m] = imx_clk_fixed_factor("pll2_main", "fast_clk", 22, 1); > + clk[pll2_pfd1_500m] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_528_BASE, 0); > + clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_528_BASE, 1); > + clk[pll2_pfd3_339m] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_528_BASE, 2); > + clk[pll2_pfd4_413m] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_528_BASE, 3); > + > + clk[pll3_main_480m] = imx_clk_fixed_factor("pll3_main", "fast_clk", 20, 1); > + clk[pll4_main] = imx_clk_fixed_factor("pll4_main", "fast_clk", 25, 1); > + /* Enet pll: fixed 50Mhz */ > + clk[pll5_main] = imx_clk_fixed_factor("pll5_main", "fast_clk", 125, 6); > + clk[enet_50m] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); > + clk[enet_25m] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); > + /* Video pll: default 960Mhz */ > + clk[pll6_main] = imx_clk_fixed_factor("pll6_main", "fast_clk", 40, 1); > + clk[pll1_sw] = imx_clk_mux("pll1_sw", CCM_CCSR, 16, 3, pll1_pfd_sel, 5); > + clk[pll2_sw] = imx_clk_mux("pll2_sw", CCM_CCSR, 19, 3, pll2_pfd_sel, 5); > + clk[sys_sw] = imx_clk_mux("sys_sw", CCM_CCSR, 0, 3, sys_clk_sel, ARRAY_SIZE(sys_clk_sel)); > + clk[ddr_sw] = imx_clk_mux("ddr_sw", CCM_CCSR, 6, 1, ddr_clk_sel, ARRAY_SIZE(ddr_clk_sel)); > + clk[sys_bus_clk] = imx_clk_divider("sys_bus", "sys_sw", CCM_CACRR, 0, 3); > + clk[platform_bus_clk] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); > + clk[ipg_bus_clk] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); > + > + clk[pll3_main_div] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); > + clk[pll4_main_div] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, > + CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); > + clk[pll6_main_div] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); > + > + clk[usbc0_clk] = imx_clk_gate2("usbc0_clk", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); > + clk[usbc1_clk] = imx_clk_gate2("usbc1_clk", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); > + > + clk[qspi0_sw] = imx_clk_mux("qspi0_sw", CCM_CSCMR1, 22, 2, qspi_clk_sel, 4); > + clk[qspi0_x4_div] = imx_clk_divider("qspi0_x4", "qspi0_sw", CCM_CSCDR3, 0, 2); > + clk[qspi0_x2_div] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); > + clk[qspi0_x1_div] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); > + clk[qspi0_gate] = imx_clk_gate("qspi0_gate", "qspi0_x1", CCM_CSCDR3, 4); > + clk[qspi0_clk] = imx_clk_gate2("qspi0_clk", "qspi0_en", CCM_CCGR2, CCM_CCGRx_CGn(4)); > + > + clk[qspi1_sw] = imx_clk_mux("qspi1_sw", CCM_CSCMR1, 24, 2, qspi_clk_sel, 4); > + clk[qspi1_x4_div] = imx_clk_divider("qspi1_x4", "qspi1_sw", CCM_CSCDR3, 8, 2); > + clk[qspi1_x2_div] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); > + clk[qspi1_x1_div] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); > + clk[qspi1_gate] = imx_clk_gate("qspi1_gate", "qspi1_x1", CCM_CSCDR3, 12); > + clk[qspi1_clk] = imx_clk_gate2("qspi1_clk", "qspi1_en", CCM_CCGR8, CCM_CCGRx_CGn(4)); > + > + clk[enet_clk_sw] = imx_clk_mux("enet_sw", CCM_CSCMR2, 4, 2, rmii_clk_sel, 4); > + clk[enet_ts_sw] = imx_clk_mux("enet_ts_sw", CCM_CSCMR2, 0, 3, enet_ts_clk_sel, 7); > + clk[enet_clk] = imx_clk_gate("enet_clk", "enet_sw", CCM_CSCDR1, 24); > + clk[enet_ts] = imx_clk_gate("enet_ts_clk", "enet_ts_sw", CCM_CSCDR1, 23); > + > + clk[pit_clk] = imx_clk_gate2("pit_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); > + > + clk[uart0_clk] = imx_clk_gate2("uart0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); > + clk[uart1_clk] = imx_clk_gate2("uart1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); > + clk[uart2_clk] = imx_clk_gate2("uart2_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); > + clk[uart3_clk] = imx_clk_gate2("uart3_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); > + > + clk[i2c0_clk] = imx_clk_gate2("i2c0_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); > + clk[i2c1_clk] = imx_clk_gate2("i2c1_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); > + > + clk[dspi0_clk] = imx_clk_gate2("dspi0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); > + clk[dspi1_clk] = imx_clk_gate2("dspi1_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); > + clk[dspi2_clk] = imx_clk_gate2("dspi2_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); > + clk[dspi3_clk] = imx_clk_gate2("dspi3_clk", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); > + > + clk[wdt_clk] = imx_clk_gate2("wdt_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); > + > + clk[esdhc0_sw] = imx_clk_mux("esdhc0_sw", CCM_CSCMR1, 16, 2, esdhc_clk_sel, 4); > + clk[esdhc0_gate] = imx_clk_gate("esdhc0_gate", "esdhc0_sw", CCM_CSCDR2, 28); > + clk[esdhc0_div] = imx_clk_divider("esdhc0_div", "esdhc0_gate", CCM_CSCDR2, 16, 4); > + clk[esdhc0_clk] = imx_clk_gate2("eshc0_clk", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); > + > + clk[esdhc1_sw] = imx_clk_mux("esdhc1_sw", CCM_CSCMR1, 18, 2, esdhc_clk_sel, 4); > + clk[esdhc1_gate] = imx_clk_gate("esdhc1_gate", "esdhc1_sw", CCM_CSCDR2, 29); > + clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc1_gate", CCM_CSCDR2, 20, 4); > + clk[esdhc1_clk] = imx_clk_gate2("eshc1_clk", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); > + > + /* > + * ftm_ext_clk and ftm_fix_clk are FTM timer counter's > + * selectable clock source, both use a common gate bit > + * in CCM_CSCDR1, select "dummy" as "ftm0_ext_fix_gate" > + * parent make the gate doesn't provids any clock freq > + * except for gate/ungate. > + */ > + clk[ftm0_ext_sw] = imx_clk_mux("ftm0_ext_sw", CCM_CSCMR2, 6, 2, ftm_ext_clk_sel, 4); > + clk[ftm0_fix_sw] = imx_clk_mux("ftm0_fix_sw", CCM_CSCMR2, 14, 1, ftm_fix_clk_sel, 2); > + clk[ftm0_ext_fix_gate] = imx_clk_gate("ftm0_ext_fix_gate", "dummy", CCM_CSCDR1, 25); > + /* ftm(n)_clk are FTM module operation clock */ > + clk[ftm0_clk] = imx_clk_gate2("ftm0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); > + clk[ftm1_clk] = imx_clk_gate2("ftm1_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); > + clk[ftm2_clk] = imx_clk_gate2("ftm2_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); > + clk[ftm3_clk] = imx_clk_gate2("ftm3_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); > + > + clk[dcu0_sw] = imx_clk_mux("dcu0_sw", CCM_CSCMR1, 28, 1, dcu_clk_sel, 2); > + clk[dcu0_gate] = imx_clk_gate("dcu0_gate", "dcu0_sw", CCM_CSCDR3, 19); > + clk[dcu0_div] = imx_clk_divider("dcu0_div", "dcu0_gate", CCM_CSCDR3, 16, 3); > + clk[dcu0_clk] = imx_clk_gate2("dcu0_clk", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); > + clk[dcu1_sw] = imx_clk_mux("dcu1_sw", CCM_CSCMR1, 29, 1, dcu_clk_sel, 2); > + clk[dcu1_gate] = imx_clk_gate("dcu1_gate", "dcu1_sw", CCM_CSCDR3, 23); > + clk[dcu1_div] = imx_clk_divider("dcu1_div", "dcu1_gate", CCM_CSCDR3, 20, 3); > + clk[dcu1_clk] = imx_clk_gate2("dcu1_clk", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); > + > + clk[esai_sw] = imx_clk_mux("esai_sw", CCM_CSCMR1, 20, 2, esai_clk_sel, 4); > + clk[esai_gate] = imx_clk_gate("esai_gate", "esai_sw", CCM_CSCDR2, 30); > + clk[esai_div] = imx_clk_divider("esai_div", "esai_gate", CCM_CSCDR2, 24, 4); > + clk[esai_clk] = imx_clk_gate2("esai_clk", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); > + > + clk[sai0_sw] = imx_clk_mux("sai0_sw", CCM_CSCMR1, 0, 2, sai_clk_sel, 4); > + clk[sai0_gate] = imx_clk_gate("sai0_gate", "sai0_sw", CCM_CSCDR1, 16); > + clk[sai0_div] = imx_clk_divider("sai0_div", "sai0_gate", CCM_CSCDR1, 0, 4); > + clk[sai0_clk] = imx_clk_gate2("sai0_clk", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); > + > + clk[sai1_sw] = imx_clk_mux("sai1_sw", CCM_CSCMR1, 2, 2, sai_clk_sel, 4); > + clk[sai1_gate] = imx_clk_gate("sai1_gate", "sai1_sw", CCM_CSCDR1, 17); > + clk[sai1_div] = imx_clk_divider("sai1_div", "sai1_gate", CCM_CSCDR1, 4, 4); > + clk[sai1_clk] = imx_clk_gate2("sai1_clk", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); > + > + clk[sai2_sw] = imx_clk_mux("sai2_sw", CCM_CSCMR1, 4, 2, sai_clk_sel, 4); > + clk[sai2_gate] = imx_clk_gate("sai2_gate", "sai2_sw", CCM_CSCDR1, 18); > + clk[sai2_div] = imx_clk_divider("sai2_div", "sai2_gate", CCM_CSCDR1, 8, 4); > + clk[sai2_clk] = imx_clk_gate2("sai2_clk", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); > + > + clk[sai3_sw] = imx_clk_mux("sai3_sw", CCM_CSCMR1, 6, 2, sai_clk_sel, 4); > + clk[sai3_gate] = imx_clk_gate("sai3_gate", "sai3_sw", CCM_CSCDR1, 19); > + clk[sai3_div] = imx_clk_divider("sai3_div", "sai3_gate", CCM_CSCDR1, 12, 4); > + clk[sai3_clk] = imx_clk_gate2("sai3_clk", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); > + > + clk[nfc_sw] = imx_clk_mux("nfc_sw", CCM_CSCMR1, 12, 2, nfc_clk_sel, 4); > + clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_sw", CCM_CSCDR2, 9); > + clk[nfc_pre_div] = imx_clk_divider("nfc_pre_div", "nfc_gate", CCM_CSCDR3, 13, 3); > + clk[nfc_frac_div] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); > + clk[nfc_clk] = imx_clk_gate2("nfc_clk", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); > + > + clk[gpu_sw] = imx_clk_mux("gpu_sw", CCM_CSCMR1, 14, 1, gpu_clk_sel, 2); > + clk[gpu_gate] = imx_clk_gate("gpu_gate", "gpu_sw", CCM_CSCDR2, 10); > + clk[gpu2d_clk] = imx_clk_gate2("gpu_clk", "gpu_gate", CCM_CCGR8, CCM_CCGRx_CGn(15)); > + > + clk[vadc_sw] = imx_clk_mux("vadc_sw", CCM_CSCMR1, 8, 2, vadc_clk_sel, 3); > + clk[vadc_gate] = imx_clk_gate("vadc_gate", "vadc_sw", CCM_CSCDR1, 22); > + clk[vadc_div] = imx_clk_divider("vadc_div", "vadc_gate", CCM_CSCDR1, 20, 2); > + clk[vadc_div_half] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); > + clk[vadc_clk] = imx_clk_gate2("vadc_clk", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); > + > + clk[adc0_clk] = imx_clk_gate2("adc0_clk", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); > + clk[adc1_clk] = imx_clk_gate2("adc1_clk", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); > + clk[dac0_clk] = imx_clk_gate2("dac0_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); > + clk[dac1_clk] = imx_clk_gate2("dac1_clk", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); > + > + clk[asrc_clk] = imx_clk_gate2("asrc_clk", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); > + > + clk[flexcan0_clk] = imx_clk_gate2("flexcan0_clk", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); > + clk[flexcan1_clk] = imx_clk_gate2("flexcan1_clk", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); > + > + clk_set_parent(clk[qspi0_sw], clk[pll1_pfd4_528m]); > + clk_set_rate(clk[qspi0_x4_div], clk_get_rate(clk[qspi0_x4_div]->parent) / 2); > + clk_set_rate(clk[qspi0_x2_div], clk_get_rate(clk[qspi0_x2_div]->parent) / 2); > + clk_set_rate(clk[qspi0_x1_div], clk_get_rate(clk[qspi0_x1_div]->parent) / 2); > + > + clk_set_parent(clk[qspi1_sw], clk[pll1_pfd4_528m]); > + clk_set_rate(clk[qspi1_x4_div], clk_get_rate(clk[qspi1_x4_div]->parent) / 2); > + clk_set_rate(clk[qspi1_x2_div], clk_get_rate(clk[qspi1_x2_div]->parent) / 2); > + clk_set_rate(clk[qspi1_x1_div], clk_get_rate(clk[qspi1_x1_div]->parent) / 2); > + > + clk_set_parent(clk[sai0_gate], clk[audio_ext]); > + clk_set_parent(clk[sai1_gate], clk[audio_ext]); > + clk_set_parent(clk[sai2_gate], clk[audio_ext]); > + clk_set_parent(clk[sai3_gate], clk[audio_ext]); > + > + /* Add the clocks to provider list */ > + clk_data.clks = clk; > + clk_data.clk_num = ARRAY_SIZE(clk); > + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > + > + return 0; > +} > diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h > index 4cba7db..683c4f4 100644 > --- a/arch/arm/mach-imx/common.h > +++ b/arch/arm/mach-imx/common.h > @@ -68,6 +68,7 @@ extern int mx31_clocks_init_dt(void); > extern int mx51_clocks_init_dt(void); > extern int mx53_clocks_init_dt(void); > extern int mx6q_clocks_init(void); > +extern int mvf_clocks_init(void); > extern struct platform_device *mxc_register_gpio(char *name, int id, > resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); > extern void mxc_set_cpu_type(unsigned int type); > diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c > new file mode 100644 > index 0000000..56d3fb0 > --- /dev/null > +++ b/arch/arm/mach-imx/mach-mvf600.c > @@ -0,0 +1,118 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include <linux/types.h> > +#include <linux/sched.h> > +#include <linux/delay.h> > +#include <linux/pm.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/irq.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/of_platform.h> > +#include <linux/init.h> > +#include <linux/clk.h> > +#include <linux/clkdev.h> > +#include <linux/clocksource.h> > +#include <linux/platform_device.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/arm-gic.h> > +#include <asm/memory.h> > +#include <asm/irq.h> > +#include <asm/setup.h> > +#include <asm/mach-types.h> > +#include <asm/mach/arch.h> > +#include <asm/mach/time.h> > +#include <asm/hardware/cache-l2x0.h> > +#include <asm/system_misc.h> Please check if you really need all these headers. > + > +#include "common.h" > + > + > +void mvf_restart(char mode, const char *cmd) > +{ > + struct device_node *np; > + void __iomem *wdog_base; > + struct clk *wdog_clk; > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt"); > + wdog_base = of_iomap(np, 0); > + if (!wdog_base) > + goto soft; > + > + wdog_clk = of_clk_get_by_name(np, "wdog"); > + if (!IS_ERR(wdog_clk)) > + clk_prepare_enable(wdog_clk); > + > + /* enable wdog */ > + writew_relaxed(1 << 2, wdog_base); > + > + /* wait for reset to assert ... */ > + mdelay(500); > + > + pr_err("Watchdog reset failed to assert reset\n"); > + > + /* delay to allow the serial port to show the message */ > + mdelay(50); > + > +soft: > + /* we'll take a jump through zero as a poor second */ > + soft_restart(0); > +} If mvf600 uses the same wdt IP block as imx, we should make this restart routine a common function to be used on mvf600, imx6q and imx6sl etc. > + > +static void __init mvf_init_machine(void) > +{ > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > +} > + > +static void __init mvf_of_init_irq(void) MVF is a DT/OF only platform, so name mvf_init_irq is just good. > +{ > + struct device_node *np; > + void __iomem *mscm_base; > + int i; > + > + l2x0_of_init(0, ~0UL); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-mscm"); > + mscm_base = of_iomap(np, 0); > + if (!mscm_base) > + return; > + > + /* route each shared peripheral interrupt to CP0 */ > + for (i = 0; i < 111; i++) > + __raw_writew(1, mscm_base + 0x880 + 2 * i); > + > + iounmap(mscm_base); > + > + irqchip_init(); > +} > + > +static void __init mvf_timer_init(void) > +{ > + mvf_clocks_init(); > + clocksource_of_init(); > +} > + > +/* > + * initialize __mach_desc_ data structure. > + */ The comment does not help too much. > +static const char *mvf_dt_compat[] __initdata = { > + "fsl,mvf600", > + NULL, > +}; > + > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid Family (Device Tree)") The string should specify a SoC rather than a Family. > + .init_irq = mvf_of_init_irq, > + .init_machine = mvf_init_machine, > + .init_time = mvf_timer_init, We generally sort these hooks in the sequence of call time. That said, the .init_time should be put before .init_machine. Shawn > + .dt_compat = mvf_dt_compat, > + .restart = mvf_restart, > +MACHINE_END > diff --git a/arch/arm/mach-imx/pit.c b/arch/arm/mach-imx/pit.c > new file mode 100644 > index 0000000..e2df0e5 > --- /dev/null > +++ b/arch/arm/mach-imx/pit.c > @@ -0,0 +1,244 @@ > +/* > + * Copyright 2012-2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + */ > + > +#include <linux/interrupt.h> > +#include <linux/irq.h> > +#include <linux/clockchips.h> > +#include <linux/clocksource.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <asm/mach/time.h> > +#include <asm/sched_clock.h> > + > + > +#define PITMCR 0x00 > +#define PITLTMR64H 0xE0 > +#define PITLTMR64L 0xE4 > + > +#define PITLDVAL 0x00 > +#define PITCVAL 0x04 > +#define PITTCTRL 0x08 > +#define PITTFLG 0x0C > + > +/* > + * Vybrid has 8 pit timers: pit0 - pit7, > + * Each memory mapped register occupy 0x10 Bytes > + */ > +#define PITOFFSET0 0x100 > +#define PITOFFSETx(n) (PITOFFSET0 + 0x10 * n) > + > +/* bit definitation */ > +#define PITMCR_MDIS (1 << 1) > +#define PITMCR_FRZ (1 << 0) > + > +#define PITTCTRL_TEN (1 << 0) > +#define PITTCTRL_TIE (1 << 1) > +#define PITCTRL_CHN (1 << 2) > + > +#define PITTFLG_TIF 0x1 > + > +static struct clock_event_device clockevent_pit; > +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; > + > +static void __iomem *clksrc_base; > +static void __iomem *clkevt_base; > +static void __iomem *sched_clock_reg; > +static unsigned long pit_cycle_per_jiffy; > + > +static inline void pit_timer_enable(void) > +{ > + __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); > +} > + > +static inline void pit_timer_disable(void) > +{ > + __raw_writel(0, clkevt_base + PITTCTRL); > +} > + > +static inline void pit_irq_disable(void) > +{ > + unsigned long val; > + > + val = __raw_readl(clkevt_base + PITTCTRL); > + val &= ~PITTCTRL_TIE; > + __raw_writel(val, clkevt_base + PITTCTRL); > +} > + > +static inline void pit_irq_enable(void) > +{ > + unsigned long val; > + > + val = __raw_readl(clkevt_base + PITTCTRL); > + val |= PITTCTRL_TIE; > + __raw_writel(val, clkevt_base + PITTCTRL); > +} > + > +static void pit_irq_acknowledge(void) > +{ > + __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); > +} > + > +static unsigned int mvf_read_sched_clock(void) > +{ > + return __raw_readl(sched_clock_reg); > +} > + > + > +static int __init pit_clocksource_init(struct clk *pit_clk) > +{ > + unsigned int c = clk_get_rate(pit_clk); > + > + sched_clock_reg = clksrc_base + PITCVAL; > + > + setup_sched_clock(mvf_read_sched_clock, 32, c); > + return clocksource_mmio_init(clksrc_base + PITCVAL, "pit", c, 300, 32, > + clocksource_mmio_readl_down); > +} > + > +/* set clock event */ > +static int pit_set_next_event(unsigned long delta, > + struct clock_event_device *unused) > +{ > + pit_timer_disable(); > + __raw_writel(delta - 1, clkevt_base + PITLDVAL); > + pit_irq_acknowledge(); > + pit_timer_enable(); > + > + return 0; > +} > + > +static void pit_set_mode(enum clock_event_mode mode, > + struct clock_event_device *evt) > +{ > + unsigned long flags; > + > + local_irq_save(flags); > + > + pit_timer_disable(); > + pit_irq_acknowledge(); > + > + /* Remember timer mode */ > + clockevent_mode = mode; > + local_irq_restore(flags); > + > + switch (mode) { > + case CLOCK_EVT_MODE_PERIODIC: > + > + __raw_writel(pit_cycle_per_jiffy - 1, clkevt_base + PITLDVAL); > + pit_timer_enable(); > + > + break; > + case CLOCK_EVT_MODE_ONESHOT: > + > + break; > + case CLOCK_EVT_MODE_SHUTDOWN: > + case CLOCK_EVT_MODE_UNUSED: > + case CLOCK_EVT_MODE_RESUME: > + > + break; > + default: > + WARN(1, "%s: unhandled event mode %d\n", __func__, mode); > + break; > + } > +} > + > +/* > + * interrupt handler for the timer > + */ > +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) > +{ > + struct clock_event_device *evt = &clockevent_pit; > + > + pit_irq_acknowledge(); > + > + if (clockevent_mode == CLOCK_EVT_MODE_ONESHOT) > + pit_timer_disable(); > + > + evt->event_handler(evt); > + > + return IRQ_HANDLED; > +} > + > +static struct irqaction pit_timer_irq = { > + .name = "MVF PIT Timer Tick", > + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, > + .handler = pit_timer_interrupt, > +}; > + > +static struct clock_event_device clockevent_pit = { > + .name = "pit", > + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, > + .set_mode = pit_set_mode, > + .set_next_event = pit_set_next_event, > + .rating = 300, > +}; > + > +static int __init pit_clockevent_init(struct clk *pit_clk) > +{ > + unsigned int c = clk_get_rate(pit_clk); > + > + clockevent_pit.cpumask = cpumask_of(0); > + clockevents_config_and_register(&clockevent_pit, c, 0x100, 0xffffff00); > + > + return 0; > +} > + > +static void __init pit_timer_init(struct device_node *np) > +{ > + struct clk *pit_clk; > + void __iomem *timer_base; > + int irq; > + > + if (!np) { > + pr_err("Failed to find pit DT node\n"); > + BUG(); > + } > + > + timer_base = of_iomap(np, 0); > + WARN_ON(!timer_base); > + > + /* chose PIT2 as clocksource, PIT3 as clockevent dev */ > + clksrc_base = timer_base + PITOFFSETx(2); > + clkevt_base = timer_base + PITOFFSETx(3); > + > + irq = irq_of_parse_and_map(np, 0); > + > + pit_clk = of_clk_get_by_name(np, "pit"); > + if (IS_ERR(pit_clk)) { > + pr_err("Vybrid PIT timer: unable to get clk\n"); > + return; > + } > + > + clk_prepare_enable(pit_clk); > + > + pit_cycle_per_jiffy = clk_get_rate(pit_clk)/(HZ); > + > + /* > + * Initialise to a known state (all timers off, and timing reset) > + */ > + __raw_writel(0x0, timer_base + PITMCR); > + > + __raw_writel(0, clkevt_base + PITTCTRL); > + __raw_writel(0xffffffff, clkevt_base + PITLDVAL); > + > + __raw_writel(0, clksrc_base + PITTCTRL); > + __raw_writel(0xffffffff, clksrc_base + PITLDVAL); > + __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); > + > + pit_clocksource_init(pit_clk); > + > + setup_irq(irq, &pit_timer_irq); > + > + pit_clockevent_init(pit_clk); > +} > + > +CLOCKSOURCE_OF_DECLARE(mvf600, "fsl,mvf-pit", pit_timer_init); > -- > 1.8.0 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-03 7:41 ` Shawn Guo @ 2013-05-08 7:26 ` Lu Jingchang-B35083 2013-05-08 14:38 ` Shawn Guo 0 siblings, 1 reply; 13+ messages in thread From: Lu Jingchang-B35083 @ 2013-05-08 7:26 UTC (permalink / raw) To: linux-arm-kernel >-----Original Message----- >From: Shawn Guo [mailto:shawn.guo at linaro.org] >Sent: Friday, May 03, 2013 3:41 PM >To: Lu Jingchang-B35083 >Cc: linux-arm-kernel at lists.infradead.org; s.hauer at pengutronix.de >Subject: Re: [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support > >> --git a/arch/arm/mach-imx/mach-mvf600.c >> b/arch/arm/mach-imx/mach-mvf600.c new file mode 100644 index >> 0000000..56d3fb0 >> --- /dev/null >> +++ b/arch/arm/mach-imx/mach-mvf600.c >> @@ -0,0 +1,118 @@ >> +/* >> + * Copyright 2012-2013 Freescale Semiconductor, Inc. >> + * >> + * This program is free software; you can redistribute it and/or >> +modify >> + * it under the terms of the GNU General Public License as published >> +by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + */ >> + >> +#include <linux/types.h> >> +#include <linux/sched.h> >> +#include <linux/delay.h> >> +#include <linux/pm.h> >> +#include <linux/interrupt.h> >> +#include <linux/io.h> >> +#include <linux/irq.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/of_irq.h> >> +#include <linux/of_platform.h> >> +#include <linux/init.h> >> +#include <linux/clk.h> >> +#include <linux/clkdev.h> >> +#include <linux/clocksource.h> >> +#include <linux/platform_device.h> >> +#include <linux/irqchip.h> >> +#include <linux/irqchip/arm-gic.h> >> +#include <asm/memory.h> >> +#include <asm/irq.h> >> +#include <asm/setup.h> >> +#include <asm/mach-types.h> >> +#include <asm/mach/arch.h> >> +#include <asm/mach/time.h> >> +#include <asm/hardware/cache-l2x0.h> >> +#include <asm/system_misc.h> > >Please check if you really need all these headers. > >> + >> +#include "common.h" >> + >> + >> +void mvf_restart(char mode, const char *cmd) { >> + struct device_node *np; >> + void __iomem *wdog_base; >> + struct clk *wdog_clk; >> + >> + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt"); >> + wdog_base = of_iomap(np, 0); >> + if (!wdog_base) >> + goto soft; >> + >> + wdog_clk = of_clk_get_by_name(np, "wdog"); >> + if (!IS_ERR(wdog_clk)) >> + clk_prepare_enable(wdog_clk); >> + >> + /* enable wdog */ >> + writew_relaxed(1 << 2, wdog_base); >> + >> + /* wait for reset to assert ... */ >> + mdelay(500); >> + >> + pr_err("Watchdog reset failed to assert reset\n"); >> + >> + /* delay to allow the serial port to show the message */ >> + mdelay(50); >> + >> +soft: >> + /* we'll take a jump through zero as a poor second */ >> + soft_restart(0); >> +} > >If mvf600 uses the same wdt IP block as imx, we should make this restart >routine a common function to be used on mvf600, imx6q and imx6sl etc. > [Lu Jingchang-B35083] Do you have plan to update the mxc_restart() function in system.c? We once used that common function for mvf600. But now this function cannot be used for mvf600 as the new clock framwork used. On the other hand, even we udpated the clk_get for the the common mxc_restart() funciton. different with i.MX6, the MVF600 need to enable the clock before using the wdt module, we still need some clue code for i.mx and mvf600. So I suggest keep the restart function for mvf600 currently. Thanks. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-08 7:26 ` Lu Jingchang-B35083 @ 2013-05-08 14:38 ` Shawn Guo 0 siblings, 0 replies; 13+ messages in thread From: Shawn Guo @ 2013-05-08 14:38 UTC (permalink / raw) To: linux-arm-kernel On Wed, May 08, 2013 at 07:26:04AM +0000, Lu Jingchang-B35083 wrote: > >If mvf600 uses the same wdt IP block as imx, we should make this restart > >routine a common function to be used on mvf600, imx6q and imx6sl etc. > > > [Lu Jingchang-B35083] > Do you have plan to update the mxc_restart() function in system.c? Yes, I plan to update it to support DT platforms. > We once used that common function for mvf600. But now this function cannot be used for mvf600 as the new clock framwork used. > On the other hand, even we udpated the clk_get for the the common mxc_restart() funciton. different with i.MX6, the MVF600 need to enable the clock before using the wdt module, we still need some clue code for i.mx and mvf600. So I suggest keep the restart function for mvf600 currently. Thanks. > Ok, you can keep it for mvf600 and I will consolidate it to use mxc_restart() later. But please make the compatible looks like the following, so that mxc_restart() will look for "fsl,imx21-wdt" to find the node in device tree. compatible = "fsl,mvf600-wdt", "fsl,imx21-wdt" Shawn ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu ` (2 preceding siblings ...) 2013-05-03 7:41 ` Shawn Guo @ 2013-05-08 18:03 ` Russell King - ARM Linux 3 siblings, 0 replies; 13+ messages in thread From: Russell King - ARM Linux @ 2013-05-08 18:03 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 02, 2013 at 03:38:04PM +0800, Jingchang Lu wrote: > +void mvf_restart(char mode, const char *cmd) > +{ > + struct device_node *np; > + void __iomem *wdog_base; > + struct clk *wdog_clk; > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf-wdt"); > + wdog_base = of_iomap(np, 0); > + if (!wdog_base) > + goto soft; > + > + wdog_clk = of_clk_get_by_name(np, "wdog"); > + if (!IS_ERR(wdog_clk)) > + clk_prepare_enable(wdog_clk); I just spotted this in another email. This is _not_ going to work reliably. This path gets called from all sorts of contexts, including when the system has crashed. It can also be called from unschedulable contexts - and the above functions _will_ trigger might_sleep() warnings as a result. The only solution to this is to put this setup for this in a separate function which is called at boot time. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid 2013-05-02 7:38 [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Jingchang Lu 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu @ 2013-05-02 7:38 ` Jingchang Lu 2013-05-02 8:56 ` Sascha Hauer 2013-05-06 2:38 ` Shawn Guo 2013-05-03 2:40 ` [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Shawn Guo 2 siblings, 2 replies; 13+ messages in thread From: Jingchang Lu @ 2013-05-02 7:38 UTC (permalink / raw) To: linux-arm-kernel This patch adds basic device tree source for Freescale Vybrid Family MVF600 platform and Tower development board. Signed-off-by: Xiaochun Li <b41219@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> --- V2: Add pinctrl support based on IMX new pinctrl framework arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mvf600-twr.dts | 80 ++++ arch/arm/boot/dts/mvf600.dtsi | 426 +++++++++++++++++++ 4 files changed, 1324 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h create mode 100644 arch/arm/boot/dts/mvf600-twr.dts create mode 100644 arch/arm/boot/dts/mvf600.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8fd41b3..6402f21 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ - imx6q-sbc6x.dtb + imx6q-sbc6x.dtb \ + mvf600-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h new file mode 100644 index 0000000..9fbc7a9 --- /dev/null +++ b/arch/arm/boot/dts/mvf600-pinfunc.h @@ -0,0 +1,816 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_MVF600_PINFUNC_H +#define __DTS_MVF600_PINFUNC_H + +/* + * Macro definations for MVF600 pin functions + * + * On Vybrid,pin's mux mode and pad control are in one 32-bit register. + * mux mode bits occupy bit[20:22] and pad config bits occupy bit[[0:15]. + * So the config word is a combination of mux mode and control config value. + * imx common pinctrl driver requires a tuple of six elements to + * describe a pin. The tuple for MVF600 is as below: + * <mux_reg conf_reg input_reg mux_mode|conf_val input_val mux_mode|conf_val> + */ + +#define ALT0 0x000000 +#define ALT1 0x100000 +#define ALT2 0x200000 +#define ALT3 0x300000 +#define ALT4 0x400000 +#define ALT5 0x500000 +#define ALT6 0x600000 +#define ALT7 0x700000 + + +#define MVF600_PAD_PTA6__GPIO_0(c) 0x000 0x000 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA6__RMII_CLKOUT(c) 0x000 0x000 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA6__RMII_CLKIN(c) 0x000 0x000 0x2F0 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA6__DCU1_TCON11(c) 0x000 0x000 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA6__DCU1_R2(c) 0x000 0x000 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA8__GPIO_1(c) 0x004 0x004 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA8__TCLK(c) 0x004 0x004 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA8__DCU0_R0(c) 0x004 0x004 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA8__MLB_CLK(c) 0x004 0x004 0x354 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA9__GPIO_2(c) 0x008 0x008 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA9__TDI(c) 0x008 0x008 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA9__RMII_CLKOUT(c) 0x008 0x008 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA9__RMII_CLKIN(c) 0x008 0x008 0x2F0 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA9__DCU0_R1(c) 0x008 0x008 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA9__WDOG_B(c) 0x008 0x008 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA10__GPIO_3(c) 0x00C 0x00C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA10__TDO(c) 0x00C 0x00C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA10__EXT_AUDIO_MCLK(c) 0x00C 0x00C 0x2EC (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA10__DCU0_G0(c) 0x00C 0x00C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA10__ENET_TS_CLKIN(c) 0x00C 0x00C 0x2F4 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA10__MLB_SIGNAL(c) 0x00C 0x00C 0x35C (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA11__GPIO_4(c) 0x010 0x010 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA11__TMS(c) 0x010 0x010 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA11__DCU0_G1(c) 0x010 0x010 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA11__MLB_DATA(c) 0x010 0x010 0x358 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA12__GPIO_5(c) 0x014 0x014 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA12__TRACECK(c) 0x014 0x014 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA12__EXT_AUDIO_MCLK(c) 0x014 0x014 0x2EC (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA12__VIU_DATA13(c) 0x014 0x014 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA12__I2C0_SCL(c) 0x014 0x014 0x33C (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA16__GPIO_6(c) 0x018 0x018 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA16__TRACED0(c) 0x018 0x018 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA16__USB0_VBUS_EN(c) 0x018 0x018 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA16__ADC1_SE0(c) 0x018 0x018 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA16__LCD29(c) 0x018 0x018 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA16__SAI2_TX_BCLK(c) 0x018 0x018 0x370 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA16__VIU_DATA14(c) 0x018 0x018 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA16__I2C0_SDA(c) 0x018 0x018 0x340 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA17__GPIO_7(c) 0x01C 0x01C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA17__TRACED1(c) 0x01C 0x01C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA17__USB0_VBUS_OC(c) 0x01C 0x01C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA17__ADC1_SE1(c) 0x01C 0x01C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA17__LCD30(c) 0x01C 0x01C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA17__USB0_SOF_PULSE(c) 0x01C 0x01C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA17__VIU_DATA15(c) 0x01C 0x01C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA17__I2C1_SCL(c) 0x01C 0x01C 0x344 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA18__GPIO_8(c) 0x020 0x020 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA18__TRACED2(c) 0x020 0x020 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA18__ADC0_SE0(c) 0x020 0x020 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA18__FTM1_QD_PHA(c) 0x020 0x020 0x334 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA18__LCD31(c) 0x020 0x020 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA18__SAI2_TX_DATA(c) 0x020 0x020 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA18__VIU_DATA16(c) 0x020 0x020 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA18__I2C1_SDA(c) 0x020 0x020 0x348 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA19__GPIO_9(c) 0x024 0x024 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA19__TRACED3(c) 0x024 0x024 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA19__ADC0_SE1(c) 0x024 0x024 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA19__FTM1_QD_PHB(c) 0x024 0x024 0x338 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA19__LCD32(c) 0x024 0x024 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA19__SAI2_TX_SYNC(c) 0x024 0x024 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA19__VIU_DATA17(c) 0x024 0x024 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA19__QSPI1_A_QSCK(c) 0x024 0x024 0x374 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA20__GPIO_10(c) 0x028 0x028 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA20__TRACED4(c) 0x028 0x028 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA20__LCD33(c) 0x028 0x028 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA20__UART3_TX(c) 0x028 0x028 0x394 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA20__DCU1_HSYNC(c) 0x028 0x028 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA21__GPIO_11(c) 0x02C 0x02C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA21__TRACED5(c) 0x02C 0x02C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA21__SAI2_RX_BCLK(c) 0x02C 0x02C 0x364 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA21__UART3_RX(c) 0x02C 0x02C 0x390 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA21__DCU1_VSYNC(c) 0x02C 0x02C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA22__GPIO_12(c) 0x030 0x030 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA22__TRACED6(c) 0x030 0x030 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA22__SAI2_RX_DATA(c) 0x030 0x030 0x368 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA22__I2C2_SCL(c) 0x030 0x030 0x34C (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA22__DCU1_TAG(c) 0x030 0x030 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA23__GPIO_13(c) 0x034 0x034 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA23__TRACED7(c) 0x034 0x034 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA23__SAI2_RX_SYNC(c) 0x034 0x034 0x36C (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA23__I2C2_SDA(c) 0x034 0x034 0x350 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA23__DCU1_DE(c) 0x034 0x034 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA24__GPIO_14(c) 0x038 0x038 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA24__TRACED8(c) 0x038 0x038 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA24__USB1_VBUS_EN(c) 0x038 0x038 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA24__ESDHC1_CLK(c) 0x038 0x038 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA24__DCU1_TCON4(c) 0x038 0x038 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA24__DDR_TEST_PAD_CTRL(c) 0x038 0x038 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA25__GPIO_15(c) 0x03C 0x03C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA25__TRACED9(c) 0x03C 0x03C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA25__USB1_VBUS_OC(c) 0x03C 0x03C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA25__ESDHC1_CMD(c) 0x03C 0x03C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA25__DCU1_TCON5(c) 0x03C 0x03C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA26__GPIO_16(c) 0x040 0x040 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA26__TRACED10(c) 0x040 0x040 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA26__SAI3_TX_BCLK(c) 0x040 0x040 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA26__ESDHC1_DAT0(c) 0x040 0x040 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA26__DCU1_TCON6(c) 0x040 0x040 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA27__GPIO_17(c) 0x044 0x044 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA27__TRACED11(c) 0x044 0x044 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA27__SAI3_RX_BCLK(c) 0x044 0x044 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA27__ESDHC1_DAT1(c) 0x044 0x044 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA27__DCU1_TCON7(c) 0x044 0x044 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA28__GPIO_18(c) 0x048 0x048 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA28__TRACED12(c) 0x048 0x048 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA28__SAI3_RX_DATA(c) 0x048 0x048 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA28__ENET1_1588_TMR0(c) 0x048 0x048 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA28__UART4_TX(c) 0x048 0x048 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA28__ESDHC1_DATA2(c) 0x048 0x048 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA28__DCU1_TCON8(c) 0x048 0x048 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA29__GPIO_19(c) 0x04C 0x04C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA29__TRACED13(c) 0x04C 0x04C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA29__SAI3_TX_DATA(c) 0x04C 0x04C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA29__ENET1_1588_TMR1(c) 0x04C 0x04C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA29__UART4_RX(c) 0x04C 0x04C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA29__ESDHC1_DAT3(c) 0x04C 0x04C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA29__DCU1_TCON9(c) 0x04C 0x04C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTA30__GPIO_20(c) 0x050 0x050 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA30__TRACED14(c) 0x050 0x050 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA30__SAI3_RX_SYNC(c) 0x050 0x050 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA30__ENET1_1588_TMR2(c) 0x050 0x050 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA30__UART4_RTS(c) 0x050 0x050 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA30__I2C3_SCL(c) 0x050 0x050 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA30__UART3_TX(c) 0x050 0x050 0x394 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA31__GPIO_21(c) 0x054 0x054 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA31__TRACED15(c) 0x054 0x054 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTA31__SAI3_TX_SYNC(c) 0x054 0x054 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTA31__ENET1_1588_TMR3(c) 0x054 0x054 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTA31__UART4_CTS(c) 0x054 0x054 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTA31__I2C3_SDA(c) 0x054 0x054 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTA31__UART3_RX(c) 0x054 0x054 0x390 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB0__GPIO_22(c) 0x058 0x058 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB0__FTM0_CH0(c) 0x058 0x058 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB0__ADC0_SE2(c) 0x058 0x058 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB0__TRACE_CTL(c) 0x058 0x058 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB0__LCD34(c) 0x058 0x058 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB0__SAI2_RX_BCLK(c) 0x058 0x058 0x364 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB0__VIU_DATA18(c) 0x058 0x058 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB0__QSPI1_A_QPCS0(c) 0x058 0x058 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB1__GPIO_23(c) 0x05C 0x05C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB1__FTM0_CH1(c) 0x05C 0x05C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB1__ADC0_SE3(c) 0x05C 0x05C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB1__SRC_RCON30(c) 0x05C 0x05C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB1__LCD35(c) 0x05C 0x05C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB1__SAI2_RX_DATA(c) 0x05C 0x05C 0x368 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB1__VIU_DATA19(c) 0x05C 0x05C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB1__QSPI1_A_DATA3(c) 0x05C 0x05C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB2__GPIO_24(c) 0x060 0x060 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB2__FTM0_CH2(c) 0x060 0x060 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB2__ADC1_SE2(c) 0x060 0x060 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB2__SRC_RCON31(c) 0x060 0x060 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB2__LCD36(c) 0x060 0x060 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB2__SAI2_RX_SYNC(c) 0x060 0x060 0x36C (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB2__VIDEO_IN0_DATA20(c) 0x060 0x060 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB2__QSPI1_A_DATA2(c) 0x060 0x060 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB3__GPIO_25(c) 0x064 0x064 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB3__FTM0_CH3(c) 0x064 0x064 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB3__ADC1_SE3(c) 0x064 0x064 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB3__PDB_EXTRIG(c) 0x064 0x064 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB3__LCD37(c) 0x064 0x064 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB3__VIU_DATA21(c) 0x064 0x064 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB3__QSPI1_A_DATA1(c) 0x064 0x064 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB4__GPIO_26(c) 0x068 0x068 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB4__FTM0_CH4(c) 0x068 0x068 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB4__UART1_TX(c) 0x068 0x068 0x380 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB4__ADC0_SE4(c) 0x068 0x068 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB4__LCD38(c) 0x068 0x068 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB4__VIU_FID(c) 0x068 0x068 0x3A8 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB4__VIU_DATA22(c) 0x068 0x068 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB4__QSPI1_A_DATA0(c) 0x068 0x068 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB5__GPIO_27(c) 0x06C 0x06C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB5__FTM0_CH5(c) 0x06C 0x06C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB5__UART1_RX(c) 0x06C 0x06C 0x37C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB5__ADC1_SE4(c) 0x06C 0x06C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB5__LCD39(c) 0x06C 0x06C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB5__VIU_DE(c) 0x06C 0x06C 0x3A4 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB5__QSPI1_A_DQS(c) 0x06C 0x06C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB6__GPIO_28(c) 0x070 0x070 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB6__FTM0_CH6(c) 0x070 0x070 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB6__UART1_RTS(c) 0x070 0x070 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB6__QSPI0_QPCS1_A(c) 0x070 0x070 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB6__LCD_LCD40(c) 0x070 0x070 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB6__FB_CLKOUT(c) 0x070 0x070 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB6__VIU_HSYNC(c) 0x070 0x070 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB6__UART2_TX(c) 0x070 0x070 0x38C (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB7__GPIO_29(c) 0x074 0x074 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB7__FTM0_CH7(c) 0x074 0x074 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB7__UART1_CTS(c) 0x074 0x074 0x378 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB7__QSPI0_B_QPCS1(c) 0x074 0x074 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB7__LCD41(c) 0x074 0x074 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB7__VIU_VSYNC(c) 0x074 0x074 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB7__UART2_RX(c) 0x074 0x074 0x388 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB8__GPIO_30(c) 0x078 0x078 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB8__FTM1_CH0(c) 0x078 0x078 0x32C (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB8__FTM1_QD_PHA(c) 0x078 0x078 0x334 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB8__VIU_DE(c) 0x078 0x078 0x3A4 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB8__DCU1_R6(c) 0x078 0x078 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB9__GPIO_31(c) 0x07C 0x07C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB9__FTM1_CH1(c) 0x07C 0x07C 0x330 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB9__FTM1_QD_PHB(c) 0x07C 0x07C 0x338 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB9__DCU1_R7(c) 0x07C 0x07C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB10__GPIO_32(c) 0x080 0x080 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB10__UART0_TX(c) 0x080 0x080 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB10__DCU0_TCON4(c) 0x080 0x080 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB10__VIU_DE(c) 0x080 0x080 0x3A4 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB10__CKO1(c) 0x080 0x080 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB10__ENET_TS_CLKIN(c) 0x080 0x080 0x2F4 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB11__GPIO_33(c) 0x084 0x084 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB11__UART0_RX(c) 0x084 0x084 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB11__DCU0_TCON5(c) 0x084 0x084 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB11__SNVS_ALARM_OUT_B(c) 0x084 0x084 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB11__CKO2(c) 0x084 0x084 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB11_ENET0_1588_TMR0(c) 0x084 0x084 0x304 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB12__GPIO_34(c) 0x088 0x088 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB12__UART0_RTS(c) 0x088 0x088 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB12__DSPI0_CS5(c) 0x088 0x088 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB12__DCU0_TCON6(c) 0x088 0x088 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB12__FB_AD1(c) 0x088 0x088 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB12__NMI(c) 0x088 0x088 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB12__ENET0_1588_TMR1(c) 0x088 0x088 0x308 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB13__GPIO_35(c) 0x08C 0x08C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB13__UART0_CTS(c) 0x08C 0x08C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB13__DSPI0_CS4(c) 0x08C 0x08C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB13__DCU0_TCON7(c) 0x08C 0x08C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB13__FB_AD0(c) 0x08C 0x08C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB13__TRACE_CTL(c) 0x08C 0x08C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB14__GPIO_36(c) 0x090 0x090 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB14__CAN0_RX(c) 0x090 0x090 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB14__I2C0_SCL(c) 0x090 0x090 0x33C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB14__DCU0_TCON8(c) 0x090 0x090 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB14__DCU1_PCLK(c) 0x090 0x090 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB15__GPIO_37(c) 0x094 0x094 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB15__CAN0_TX(c) 0x094 0x094 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB15__I2C0_SDA(c) 0x094 0x094 0x340 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB15__DCU0_TCON9(c) 0x094 0x094 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB15__VIU_PIX_CLK(c) 0x094 0x094 0x3AC (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB16__GPIO_38(c) 0x098 0x098 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB16__CAN1_RX(c) 0x098 0x098 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB16__I2C1_SCL(c) 0x098 0x098 0x344 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB16__DCU0_TCON10(c) 0x098 0x098 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB17__GPIO_39(c) 0x09C 0x09C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB17__CAN1_TX(c) 0x09C 0x09C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB17__I2C1_SDA(c) 0x09C 0x09C 0x348 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB17__DCU0_TCON11(c) 0x09C 0x09C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB18__GPIO_40(c) 0x0A0 0x0A0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB18__DSPI0_CS1(c) 0x0A0 0x0A0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB18__EXT_AUDIO_MCLK(c) 0x0A0 0x0A0 0x2EC (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB18__VIU_DATA9(c) 0x0A0 0x0A0 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB19__GPIO_41(c) 0x0A4 0x0A4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB19__DSPI0_CS0(c) 0x0A4 0x0A4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB19__VIU_DATA10(c) 0x0A4 0x0A4 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB20__GPIO_42(c) 0x0A8 0x0A8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB20__DSPI0_SIN(c) 0x0A8 0x0A8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB20__LCD42(c) 0x0A8 0x0A8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB20__VIU_DATA11(c) 0x0A8 0x0A8 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB21__GPIO_43(c) 0x0AC 0x0AC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB21__DSPI0_SOUT(c) 0x0AC 0x0AC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB21__LCD43(c) 0x0AC 0x0AC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB21__VIU_DATA12(c) 0x0AC 0x0AC 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB21__DCU1_PCLK(c) 0x0AC 0x0AC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB22__GPIO_44(c) 0x0B0 0x0B0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB22__DSPI0_SCK(c) 0x0B0 0x0B0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB22__VLCD(c) 0x0B0 0x0B0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB22__VIU_FID(c) 0x0B0 0x0B0 0x3A8 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC0__GPIO_45(c) 0x0B4 0x0B4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC0__ENET_RMII0_MDC(c) 0x0B4 0x0B4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC0__FTM1_CH0(c) 0x0B4 0x0B4 0x32C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC0__DSPI0_CS3(c) 0x0B4 0x0B4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC0__ESAI_SCKT(c) 0x0B4 0x0B4 0x310 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC0__ESDHC0_CLK(c) 0x0B4 0x0B4 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC0__VIU_DATA0(c) 0x0B4 0x0B4 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC0__SRC_RCON18(c) 0x0B4 0x0B4 0x398 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC1__GPIO_46(c) 0x0B8 0x0B8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC1__ENET_RMII0_MDIO(c) 0x0B8 0x0B8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC1__FTM1_CH1(c) 0x0B8 0x0B8 0x330 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC1__DSPI0_CS2(c) 0x0B8 0x0B8 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC1__ESAI_FST(c) 0x0B8 0x0B8 0x30C (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC1__ESDHC0_CMD(c) 0x0B8 0x0B8 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC1__VIU_DATA1(c) 0x0B8 0x0B8 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC1__SRC_RCON19(c) 0x0B8 0x0B8 0x39C (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC2__GPIO_47(c) 0x0BC 0x0BC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC2__ENET_RMII0_CRS(c) 0x0BC 0x0BC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC2__UART1_TX(c) 0x0BC 0x0BC 0x380 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC2__ESAI_SDO0(c) 0x0BC 0x0BC 0x314 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC2__ESDHC0_DAT0(c) 0x0BC 0x0BC 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC2__VIU_DATA2(c) 0x0BC 0x0BC 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC2__SRC_RCON20(c) 0x0BC 0x0BC 0x3A0 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC3__GPIO_48(c) 0x0C0 0x0C0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC3__ENET_RMII0_RXD1(c) 0x0C0 0x0C0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC3__UART1_RX(c) 0x0C0 0x0C0 0x37C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC3__ESAI_SDO1(c) 0x0C0 0x0C0 0x318 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC3__ESDHC0_DAT1(c) 0x0C0 0x0C0 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC3__VIU_DATA3(c) 0x0C0 0x0C0 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC3__DCU0_R0(c) 0x0C0 0x0C0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC4__GPIO_49(c) 0x0C4 0x0C4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC4__ENET_RMII0_RXD0(c) 0x0C4 0x0C4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC4__UART1_RTS(c) 0x0C4 0x0C4 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC4__DSPI1_CS1(c) 0x0C4 0x0C4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC4__ESAI_SDO2(c) 0x0C4 0x0C4 0x31C (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC4__ESDHC0_DAT2(c) 0x0C4 0x0C4 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC4__VIU_DATA4(c) 0x0C4 0x0C4 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC4__DCU0_R1(c) 0x0C4 0x0C4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC5__GPIO_50(c) 0x0C8 0x0C8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC5__ENET_RMII0_RXER(c) 0x0C8 0x0C8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC5__UART1_CTS(c) 0x0C8 0x0C8 0x378 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC5__DSPI1_CS0(c) 0x0C8 0x0C8 0x300 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC5__ESAI_SDO3(c) 0x0C8 0x0C8 0x320 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC5__ESDHC0_DAT3(c) 0x0C8 0x0C8 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC5__VIU_DATA5(c) 0x0C8 0x0C8 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC5__DCU0_G0(c) 0x0C8 0x0C8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC6__GPIO_51(c) 0x0CC 0x0CC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC6__ENET_RMII0_TXD1(c) 0x0CC 0x0CC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC6__DSPI1_SIN(c) 0x0CC 0x0CC 0x2FC (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC6__ESAI_SDI0(c) 0x0CC 0x0CC 0x328 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC6__ESDHC0_WP(c) 0x0CC 0x0CC 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC6__VIU_DATA6(c) 0x0CC 0x0CC 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC6__DCU0_G1(c) 0x0CC 0x0CC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC7__GPIO_52(c) 0x0D0 0x0D0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC7__ENET_RMII0_TXD0(c) 0x0D0 0x0D0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC7__DSPI1_SOUT(c) 0x0D0 0x0D0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC7__ESAI_SDI1(c) 0x0D0 0x0D0 0x324 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC7__VIU_DATA7(c) 0x0D0 0x0D0 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC7__DCU0_B0(c) 0x0D0 0x0D0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC8__GPIO_53(c) 0x0D4 0x0D4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC8__ENET_RMII0_TXEN(c) 0x0D4 0x0D4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC8__DSPI1_SCK(c) 0x0D4 0x0D4 0x2F8 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC8__VIU_DATA8(c) 0x0D4 0x0D4 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC8__DCU0_B1(c) 0x0D4 0x0D4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC9__GPIO_54(c) 0x0D8 0x0D8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC9__ENET_RMII1_MDC(c) 0x0D8 0x0D8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC9__ESAI_SCKT(c) 0x0D8 0x0D8 0x310 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC9__MLB_CLK(c) 0x0D8 0x0D8 0x354 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC9__DEBUG_OUT0(c) 0x0D8 0x0D8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC10__GPIO_55(c) 0x0DC 0x0DC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC10__ENET_RMII1_MDIO(c) 0x0DC 0x0DC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC10__ESAI_FST(c) 0x0DC 0x0DC 0x30C (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC10__MLB_SIGNAL(c) 0x0DC 0x0DC 0x35C (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC10__DEBUG_OUT1(c) 0x0DC 0x0DC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC11__GPIO_56(c) 0x0E0 0x0E0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC11__ENET_RMII1_CRS(c) 0x0E0 0x0E0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC11__ESAI_SDO0(c) 0x0E0 0x0E0 0x314 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC11__MLB_DATA(c) 0x0E0 0x0E0 0x358 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC11__DEBUG_OUT(c) 0x0E0 0x0E0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC12__GPIO_57(c) 0x0E4 0x0E4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC12__ENET_RMII_RXD1(c) 0x0E4 0x0E4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC12__ESAI_SDO1(c) 0x0E4 0x0E4 0x318 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC12__SAI2_TX_BCLK(c) 0x0E4 0x0E4 0x370 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC12__DEBUG_OUT3(c) 0x0E4 0x0E4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC13__GPIO_58(c) 0x0E8 0x0E8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC13__ENET_RMII1_RXD0(c) 0x0E8 0x0E8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC13__ESAI_SDO2(c) 0x0E8 0x0E8 0x31C (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC13__SAI2_RX_BCLK(c) 0x0E8 0x0E8 0x364 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC13__DEBUG_OUT4(c) 0x0E8 0x0E8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC14__GPIO_59(c) 0x0EC 0x0EC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC14__ENET_RMII1_RXER(c) 0x0EC 0x0EC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC14__ESAI_SDO3(c) 0x0EC 0x0EC 0x320 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC14__UART5_TX(c) 0x0EC 0x0EC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC14__SAI2_RX_DATA(c) 0x0EC 0x0EC 0x368 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC14__ADC0_SE6(c) 0x0EC 0x0EC 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC14__DEBUG_OUT5(c) 0x0EC 0x0EC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC15__GPIO_60(c) 0x0F0 0x0F0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC15__ENET_RMII1_TXD1(c) 0x0F0 0x0F0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC15__ESAI_SDI0(c) 0x0F0 0x0F0 0x328 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC15__UART5_RX(c) 0x0F0 0x0F0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC15__SAI2_TX_DATA(c) 0x0F0 0x0F0 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC15__ADC0_SE7(c) 0x0F0 0x0F0 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC15__DEBUG_OUT6(c) 0x0F0 0x0F0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC16__GPIO_61(c) 0x0F4 0x0F4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC16__ENET_RMII1_TXD0(c) 0x0F4 0x0F4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC16__ESAI_SDI1(c) 0x0F4 0x0F4 0x324 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC16__UART5_RTS(c) 0x0F4 0x0F4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC16__SAI2_RX_SYNC(c) 0x0F4 0x0F4 0x36C (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC16__ADC1_SE6(c) 0x0F4 0x0F4 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC16__DEBUG_OUT7(c) 0x0F4 0x0F4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC17__GPIO_62(c) 0x0F8 0x0F8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC17__ENET_RMII1_TXEN(c) 0x0F8 0x0F8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC17__ADC1_SE7(c) 0x0F8 0x0F8 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC17__UART5_CTS(c) 0x0F8 0x0F8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC17__SAI2_TX_SYNC(c) 0x0F8 0x0F8 0x374 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC17__USB1_SOF_PULSE(c) 0x0F8 0x0F8 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC17__DEBUG_OUT8(c) 0x0F8 0x0F8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD31__GPIO_63(c) 0x0FC 0x0FC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD31__FB_AD31(c) 0x0FC 0x0FC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD31__NF_IO15(c) 0x0FC 0x0FC 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD31__FTM3_CH0(c) 0x0FC 0x0FC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD31__DSPI2_CS1(c) 0x0FC 0x0FC 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD31__DEBUG_OUT9(c) 0x0FC 0x0FC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD30__GPIO_64(c) 0x100 0x100 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD30__FB_AD30(c) 0x100 0x100 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD30__NF_IO14(c) 0x100 0x100 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD30__FTM3_CH1(c) 0x100 0x100 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD30__DSPI2_CS0(c) 0x100 0x100 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD30__DEBUG_OUT10(c) 0x100 0x100 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD29__GPIO_65(c) 0x104 0x104 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD29__FB_AD29(c) 0x104 0x104 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD29__NF_IO13(c) 0x104 0x104 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD29__FTM3_CH2(c) 0x104 0x104 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD29__DSPI2_SIN(c) 0x104 0x104 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD29__DEBUG_OUT11(c) 0x104 0x104 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD28__GPIO_66(c) 0x108 0x108 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD28__FB_AD28(c) 0x108 0x108 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD28__NF_IO12(c) 0x108 0x108 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD28__I2C2_SCL(c) 0x108 0x108 0x34C (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD28__FTM3_CH3(c) 0x108 0x108 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD28__DSPI2_SOUT(c) 0x108 0x108 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD28__DEBUG_OUT12(c) 0x108 0x108 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD27__GPIO_67(c) 0x10C 0x10C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD27__FB_AD27(c) 0x10C 0x10C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD27__NF_IO11(c) 0x10C 0x10C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD27__I2C2_SDA(c) 0x10C 0x10C 0x350 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD27__FTM3_CH4(c) 0x10C 0x10C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD27__DSPI2_SCK(c) 0x10C 0x10C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD27__DEBUG_OUT13(c) 0x10C 0x10C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD26__GPIO_68(c) 0x110 0x110 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD26__FB_AD26(c) 0x110 0x110 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD26__NF_IO10(c) 0x110 0x110 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD26__FTM3_CH5(c) 0x110 0x110 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD26__ESDHC1_WP(c) 0x110 0x110 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD26__DEBUG_OUT14(c) 0x110 0x110 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD25__GPIO_69(c) 0x114 0x114 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD25__FB_AD25(c) 0x114 0x114 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD25__NF_IO9(c) 0x114 0x114 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD25__FTM3_CH6(c) 0x114 0x114 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD25__DEBUG_OUT15(c) 0x114 0x114 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD24__GPIO_70(c) 0x118 0x118 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD24__FB_AD24(c) 0x118 0x118 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD24__NF_IO8(c) 0x118 0x118 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD24__FTM3_CH7(c) 0x118 0x118 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD24__DEBUG_OUT16(c) 0x118 0x118 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD23__GPIO_71(c) 0x11C 0x11C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD23__FB_AD23(c) 0x11C 0x11C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD23__NF_IO7(c) 0x11C 0x11C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD23__FTM2_CH0(c) 0x11C 0x11C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD23__ENET0_1588_TMR0(c) 0x11C 0x11C 0x304 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD23__ESDHC0_DAT4(c) 0x11C 0x11C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD23__UART2_TX(c) 0x11C 0x11C 0x38C (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTD23__DCU1_R3(c) 0x11C 0x11C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD22__GPIO_72(c) 0x120 0x120 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD22__FB_AD22(c) 0x120 0x120 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD22__NF_IO6(c) 0x120 0x120 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD22__FTM2_CH1(c) 0x120 0x120 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD22__ENET0_1588_TMR1(c) 0x120 0x120 0x308 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD22__ESDHC0_DAT5(c) 0x120 0x120 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD22__UART2_RX(c) 0x120 0x120 0x388 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTD22__DCU1_R4(c) 0x120 0x120 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD21__GPIO_73(c) 0x124 0x124 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD21__FB_AD21(c) 0x124 0x124 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD21__NF_IO5(c) 0x124 0x124 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD21__ENET0_1588_TMR2(c) 0x124 0x124 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD21__ESDHC0_DAT6(c) 0x124 0x124 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD21__UART2_RTS(c) 0x124 0x124 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTD21__DCU1_R5(c) 0x124 0x124 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD20__GPIO_74(c) 0x128 0x128 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD20__FB_AD20(c) 0x128 0x128 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD20__NF_IO4(c) 0x128 0x128 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD20__ENET0_1588_TMR3(c) 0x128 0x128 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD20__ESDHC0_DAT7(c) 0x128 0x128 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD20__UART2_CTS(c) 0x128 0x128 0x384 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTD20__DCU1_R0(c) 0x128 0x128 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD19__GPIO_75(c) 0x12C 0x12C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD19__FB_AD19(c) 0x12C 0x12C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD19__NF_IO3(c) 0x12C 0x12C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD19__ESAI_SCKR(c) 0x12C 0x12C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD19__I2C0_SCL(c) 0x12C 0x12C 0x33C (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD19__FTM2_QD_PHA(c) 0x12C 0x12C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD19__DCU1_R1(c) 0x12C 0x12C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD18__GPIO_76(c) 0x130 0x130 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD18__FB_AD18(c) 0x130 0x130 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD18__NF_IO2(c) 0x130 0x130 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD18__ESAI_FSR(c) 0x130 0x130 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD18__I2C0_SDA(c) 0x130 0x130 0x340 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD18__FTM2_QD_PHB(c) 0x130 0x130 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD18__DCU1_G0(c) 0x130 0x130 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD17__GPIO_77(c) 0x134 0x134 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD17__FB_AD17(c) 0x134 0x134 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD17__NF_IO1(c) 0x134 0x134 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD17__ESAI_HCKR(c) 0x134 0x134 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD17__I2C1_SCL(c) 0x134 0x134 0x344 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD17__DCU1_G1(c) 0x134 0x134 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD16__GPIO_78(c) 0x138 0x138 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD16__FB_AD16(c) 0x138 0x138 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD16__NF_IO0(c) 0x138 0x138 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD16__ESAI_HCKT(c) 0x138 0x138 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD16__I2C1_SDA(c) 0x138 0x138 0x348 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD16__DCU1_G2(c) 0x138 0x138 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD0__GPIO_79(c) 0x13C 0x13C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD0__QSPI0_A_QSCK(c) 0x13C 0x13C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD0__UART2_TX(c) 0x13C 0x13C 0x38C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD0__FB_AD15(c) 0x13C 0x13C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD0__SPDIF_EXTCLK(c) 0x13C 0x13C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD0__DEBUG_OUT17(c) 0x13C 0x13C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD1__GPIO_80(c) 0x140 0x140 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD1__QSPI0_A_CS0(c) 0x140 0x140 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD1__UART2_RX(c) 0x140 0x140 0x388 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD1__FB_AD14(c) 0x140 0x140 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD1__SPDIF_IN1(c) 0x140 0x140 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD1__DEBUG_OUT18(c) 0x140 0x140 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD2__GPIO_81(c) 0x144 0x144 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD2__QSPI0_A_DATA3(c) 0x144 0x144 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD2__UART2_RTS(c) 0x144 0x144 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD2__DSPI1_CS3(c) 0x144 0x144 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD2__FB_AD13(c) 0x144 0x144 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD2__SPDIF_OUT1(c) 0x144 0x144 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD2__DEBUG_OUT19(c) 0x144 0x144 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD3__GPIO_82(c) 0x148 0x148 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD3__QSPI0_A_DATA2(c) 0x148 0x148 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD3__UART2_CTS(c) 0x148 0x148 0x384 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD3__DSPI1_CS2(c) 0x148 0x148 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD3__FB_AD12(c) 0x148 0x148 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD3__SPDIF_PLOCK(c) 0x148 0x148 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD3__DEBUG_OUT20(c) 0x148 0x148 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD4__GPIO_83(c) 0x14C 0x14C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD4__QSPI0_A_DATA1(c) 0x14C 0x14C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD4__DSPI1_CS1(c) 0x14C 0x14C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD4__FB_AD11(c) 0x14C 0x14C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD4__SPDIF_SRCLK(c) 0x14C 0x14C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTD4__DEBUG_OUT21(c) 0x14C 0x14C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD5__GPIO_84(c) 0x150 0x150 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD5__QSPI0_A_DATA0(c) 0x150 0x150 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD5__DSPI1_CS0(c) 0x150 0x150 0x300 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD5__FB_AD10(c) 0x150 0x150 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD5__DEBUG_OUT22(c) 0x150 0x150 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD6__GPIO_85(c) 0x154 0x154 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD6__QSPI1_A_DQS(c) 0x154 0x154 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD6__DSPI1_SIN(c) 0x154 0x154 0x2FC (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD6__FB_AD9(c) 0x154 0x154 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD6__DEBUG_OUT23(c) 0x154 0x154 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD7__GPIO_86(c) 0x158 0x158 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD7__QSPI0_B_QSCK(c) 0x158 0x158 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD7__DSPI1_SOUT(c) 0x158 0x158 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD7__FB_AD8(c) 0x158 0x158 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD7__DEBUG_OUT24(c) 0x158 0x158 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD8__GPIO_87(c) 0x15C 0x15C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD8__QSPI0_B_CS0(c) 0x15C 0x15C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD8__FB_CLKOUT(c) 0x15C 0x15C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD8__DSPI1_SCK(c) 0x15C 0x15C 0x2F8 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTD8__FB_AD7(c) 0x15C 0x15C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD8__DEBUG_OUT25(c) 0x15C 0x15C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD9__GPIO_88(c) 0x160 0x160 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD9__QSPI0_B_DATA3(c) 0x160 0x160 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD9__DSPI3_CS1(c) 0x160 0x160 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD9__FB_AD6(c) 0x160 0x160 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD9__SAI1_TX_SYNC(c) 0x160 0x160 0x360 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTD9__DCU1_B0(c) 0x160 0x160 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD10__GPIO_89(c) 0x164 0x164 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD10__QSPI0_B_DATA2(c) 0x164 0x164 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD10__DSPI3_CS0(c) 0x164 0x164 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD10__FB_AD5(c) 0x164 0x164 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD10__DCU1_B1(c) 0x164 0x164 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD11__GPIO_90(c) 0x168 0x168 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD11__QSPI0_B_DATA1(c) 0x168 0x168 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD11__DSPI3_SIN(c) 0x168 0x168 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD11__FB_AD4(c) 0x168 0x168 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD11__DEBUG_OUT26(c) 0x168 0x168 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD12__GPIO_91(c) 0x16C 0x16C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD12__QSPI0_B_DATA0(c) 0x16C 0x16C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD12__DSPI3_SOUT(c) 0x16C 0x16C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD12__FB_AD3(c) 0x16C 0x16C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD12__DEBUG_OUT27(c) 0x16C 0x16C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTD13__GPIO_92(c) 0x170 0x170 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTD13__QSPI0_B_DQS(c) 0x170 0x170 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTD13__DSPI3_SCK(c) 0x170 0x170 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTD13__FB_AD2(c) 0x170 0x170 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTD13__DEBUG_OUT28(c) 0x170 0x170 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB23__GPIO_93(c) 0x174 0x174 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB23__SAI0_TX_BCLK(c) 0x174 0x174 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB23__UART1_TX(c) 0x174 0x174 0x380 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB23__SRC_RCON18(c) 0x174 0x174 0x398 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB23__FB_MUXED_ALE(c) 0x174 0x174 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB23__FB_TS_B(c) 0x174 0x174 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB23__UART3_RTS(c) 0x174 0x174 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB23__DCU1_G3(c) 0x174 0x174 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB24__GPIO_94(c) 0x178 0x178 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB24__SAI0_RX_BCLK(c) 0x178 0x178 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB24__UART1_RX(c) 0x178 0x178 0x37C (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB24__SRC_RCON19(c) 0x178 0x178 0x39C (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB24__FB_MUXED_TSIZ0(c) 0x178 0x178 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB24__NF_WE_B(c) 0x178 0x178 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB24__UART3_CTS(c) 0x178 0x178 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB24__DCU1_G4(c) 0x178 0x178 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB25__GPIO_95(c) 0x17C 0x17C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB25__SAI0_RX_DATA(c) 0x17C 0x17C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB25__UART1_RTS(c) 0x17C 0x17C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB25__SRC_RCON20(c) 0x17C 0x17C 0x3A0 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB25__FB_CS1_B(c) 0x17C 0x17C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB25__NF_CE0_B(c) 0x17C 0x17C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB25__DCU1_G5(c) 0x17C 0x17C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB26__GPIO_96(c) 0x180 0x180 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB26__SAI0_TX_DATA(c) 0x180 0x180 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB26__UART1_CTS(c) 0x180 0x180 0x378 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTB26__SRC_RCON21(c) 0x180 0x180 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB26__FB_CS0_B(c) 0x180 0x180 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB26__NF_CE1_B(c) 0x180 0x180 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB26__DCU1_G6(c) 0x180 0x180 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB27__GPIO_97(c) 0x184 0x184 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB27__SAI0_RX_SYNC(c) 0x184 0x184 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB27__SRC_RCON22(c) 0x184 0x184 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB27__FB_OE_B(c) 0x184 0x184 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB27__FB_MUXED_TBST_B(c) 0x184 0x184 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTB27__NF_RE_B(c) 0x184 0x184 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTB27__DCU1_G7(c) 0x184 0x184 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTB28__GPIO_98(c) 0x188 0x188 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTB28__SAI0_TX_SYNC(c) 0x188 0x188 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTB28__SRC_RCON23(c) 0x188 0x188 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTB28__FB_RW_B(c) 0x188 0x188 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTB28__DCU1_B6(c) 0x188 0x188 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC26__GPIO_99(c) 0x18C 0x18C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC26__SAI1_TX_BCLK(c) 0x18C 0x18C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC26__DSPI0_CS5(c) 0x18C 0x18C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC26__SRC_RCON24(c) 0x18C 0x18C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC26__FB_TA_B(c) 0x18C 0x18C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC26__NF_RB_B(c) 0x18C 0x18C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC26__DCU1_B7(c) 0x18C 0x18C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC27__GPIO_100(c) 0x190 0x190 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC27__SAI1_RX_BCLK(c) 0x190 0x190 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC27__DSPI0_CS4(c) 0x190 0x190 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC27__SRC_RCON25(c) 0x190 0x190 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC27__FB_BE3_B(c) 0x190 0x190 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC27__FB_CS3_B(c) 0x190 0x190 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC27__NF_ALE(c) 0x190 0x190 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC27__DCU1_B2(c) 0x190 0x190 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC28__GPIO_101(c) 0x194 0x194 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC28__SAI1_RX_DATA(c) 0x194 0x194 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC28__DSPI0_CS3(c) 0x194 0x194 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC28__SRC_RCON26(c) 0x194 0x194 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC28__FB_BE2_B(c) 0x194 0x194 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC28__FB_CS2_B(c) 0x194 0x194 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC28__NF_CLE(c) 0x194 0x194 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC28__DCU1_B3(c) 0x194 0x194 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC29__GPIO_102(c) 0x198 0x198 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC29__SAI1_TX_DATA(c) 0x198 0x198 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC29__DSPI0_CS2(c) 0x198 0x198 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC29__SRC_RCON27(c) 0x198 0x198 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC29__FB_BE1_B(c) 0x198 0x198 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC29__FB_MUXED_TSIZE1(c) 0x198 0x198 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC29__DCU1_B4(c) 0x198 0x198 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC30__GPIO_103(c) 0x19C 0x19C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC30__SAI1_RX_SYNC(c) 0x19C 0x19C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC30__DSPI1_CS2(c) 0x19C 0x19C 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTC30__SRC_RCON28(c) 0x19C 0x19C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC30__FB_MUXED_BE0_B(c) 0x19C 0x19C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTC30__FB_TSIZ0(c) 0x19C 0x19C 0x000 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTC30__ADC0_SE5(c) 0x19C 0x19C 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC30__DCU1_B5(c) 0x19C 0x19C 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTC31__GPIO_104(c) 0x1A0 0x1A0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTC31__SAI1_TX_SYNC(c) 0x1A0 0x1A0 0x360 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTC31__SRC_RCON29(c) 0x1A0 0x1A0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTC31__ADC1_SE5(c) 0x1A0 0x1A0 0x000 (ALT6|c) 0 (ALT6|c) +#define MVF600_PAD_PTC31__DCU1_B6(c) 0x1A0 0x1A0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE0__GPIO_105(c) 0x1A4 0x1A4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE0__DCU0_HSYNC(c) 0x1A4 0x1A4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE0__SRC_BMODE1(c) 0x1A4 0x1A4 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTE0__LCD0(c) 0x1A4 0x1A4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE0__DEBUG_OUT29(c) 0x1A4 0x1A4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE1__GPIO_106(c) 0x1A8 0x1A8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE1__DCU0_VSYNC(c) 0x1A8 0x1A8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE1__SRC_BMODE0(c) 0x1A8 0x1A8 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTE1__LCD1(c) 0x1A8 0x1A8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE1__DEBUG_OUT30(c) 0x1A8 0x1A8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE2__GPIO_107(c) 0x1AC 0x1AC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE2__DCU0_PCLK(c) 0x1AC 0x1AC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE2__LCD2(c) 0x1AC 0x1AC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE2__DEBUG_OUT31(c) 0x1AC 0x1AC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE3__GPIO_108(c) 0x1B0 0x1B0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE3__DCU0_TAG(c) 0x1B0 0x1B0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE3__LCD3(c) 0x1B0 0x1B0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE3__DEBUG_OUT32(c) 0x1B0 0x1B0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE4__GPIO_109(c) 0x1B4 0x1B4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE4__DCU0_DE(c) 0x1B4 0x1B4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE4__LCD4(c) 0x1B4 0x1B4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE4__DEBUG_OUT33(c) 0x1B4 0x1B4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE5__GPIO_110(c) 0x1B8 0x1B8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE5__DCU0_R0(c) 0x1B8 0x1B8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE5__LCD5(c) 0x1B8 0x1B8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE5__DEBUG_OUT34(c) 0x1B8 0x1B8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE6__GPIO_111(c) 0x1BC 0x1BC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE6__DCU0_R1(c) 0x1BC 0x1BC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE6__LCD6(c) 0x1BC 0x1BC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE6__DEBUG_OUT35(c) 0x1BC 0x1BC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE7__GPIO_112(c) 0x1C0 0x1C0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE7__DCU0_R2(c) 0x1C0 0x1C0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE7__SRC_RCON0(c) 0x1C0 0x1C0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE7__LCD7(c) 0x1C0 0x1C0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE7__DEBUG_OUT36(c) 0x1C0 0x1C0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE8__GPIO_113(c) 0x1C4 0x1C4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE8__DCU0_R3(c) 0x1C4 0x1C4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE8__SRC_RCON1(c) 0x1C4 0x1C4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE8__LCD8(c) 0x1C4 0x1C4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE8__DEBUG_OUT37(c) 0x1C4 0x1C4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE9__GPIO_114(c) 0x1C8 0x1C8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE9__DCU0_R4(c) 0x1C8 0x1C8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE9__SRC_RCON2(c) 0x1C8 0x1C8 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE9__LCD9(c) 0x1C8 0x1C8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE9__DEBUG_OUT38(c) 0x1C8 0x1C8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE10__GPIO_115(c) 0x1CC 0x1CC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE10__DCU0_R5(c) 0x1CC 0x1CC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE10__SRC_RCON3(c) 0x1CC 0x1CC 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE10__LCD10(c) 0x1CC 0x1CC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE10__DEBUG_OUT39(c) 0x1CC 0x1CC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE11__GPIO_116(c) 0x1D0 0x1D0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE11__DCU0_R6(c) 0x1D0 0x1D0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE11__SRC_RCON4(c) 0x1D0 0x1D0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE11__LCD11(c) 0x1D0 0x1D0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE11__DEBUG_OUT40(c) 0x1D0 0x1D0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE12__GPIO_117(c) 0x1D4 0x1D4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE12__DCU0_R7(c) 0x1D4 0x1D4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE12__DSPI1_CS3(c) 0x1D4 0x1D4 0x000 (ALT2|c) 0 (ALT2|c) +#define MVF600_PAD_PTE12__SRC_RCON5(c) 0x1D4 0x1D4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE12__LCD12(c) 0x1D4 0x1D4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE12__LPT_ALT0(c) 0x1D4 0x1D4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE13__GPIO_118(c) 0x1D8 0x1D8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE13__DCU0_G0(c) 0x1D8 0x1D8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE13__LCD13(c) 0x1D8 0x1D8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE13__DEBUG_OUT41(c) 0x1D8 0x1D8 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE14__GPIO_119(c) 0x1DC 0x1DC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE14__DCU0_G1(c) 0x1DC 0x1DC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE14__LCD14(c) 0x1DC 0x1DC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE14__DEBUG_OUT42(c) 0x1DC 0x1DC 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE15__GPIO_120(c) 0x1E0 0x1E0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE15__DCU0_G2(c) 0x1E0 0x1E0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE15__SRC_RCON6(c) 0x1E0 0x1E0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE15__LCD15(c) 0x1E0 0x1E0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE15__DEBUG_OUT43(c) 0x1E0 0x1E0 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE16__GPIO_121(c) 0x1E4 0x1E4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE16__DCU0_G3(c) 0x1E4 0x1E4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE16__SRC_RCON7(c) 0x1E4 0x1E4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE16__LCD16(c) 0x1E4 0x1E4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE17__GPIO_122(c) 0x1E8 0x1E8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE17__DCU0_G4(c) 0x1E8 0x1E8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE17__SRC_RCON8(c) 0x1E8 0x1E8 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE17__LCD17(c) 0x1E8 0x1E8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE18__GPIO_123(c) 0x1EC 0x1EC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE18__DCU0_G5(c) 0x1EC 0x1EC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE18__SRC_RCON9(c) 0x1EC 0x1EC 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE18__LCD18(c) 0x1EC 0x1EC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE19__GPIO_124(c) 0x1F0 0x1F0 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE19__DCU0_G6(c) 0x1F0 0x1F0 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE19__SRC_RCON10(c) 0x1F0 0x1F0 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE19__LCD19(c) 0x1F0 0x1F0 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE19__I2C0_SCL(c) 0x1F0 0x1F0 0x33C (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTE20__GPIO_125(c) 0x1F4 0x1F4 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE20__DCU0_G7(c) 0x1F4 0x1F4 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE20__SRC_RCON11(c) 0x1F4 0x1F4 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE20__LCD20(c) 0x1F4 0x1F4 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE20__I2C0_SDA(c) 0x1F4 0x1F4 0x340 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTE20__EWM_IN(c) 0x1F4 0x1F4 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTE21__GPIO_126(c) 0x1F8 0x1F8 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE21__DCU0_B0(c) 0x1F8 0x1F8 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE21__LCD21(c) 0x1F8 0x1F8 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE22__GPIO_127(c) 0x1FC 0x1FC 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE22__DCU0_B1(c) 0x1FC 0x1FC 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE22__LCD22(c) 0x1FC 0x1FC 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE23__GPIO_128(c) 0x200 0x200 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE23__DCU0_B2(c) 0x200 0x200 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE23__SRC_RCON12(c) 0x200 0x200 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE23__LCD23(c) 0x200 0x200 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE24__GPIO_129(c) 0x204 0x204 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE24__DCU0_B3(c) 0x204 0x204 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE24__SRC_RCON13(c) 0x204 0x204 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE24__LCD24(c) 0x204 0x204 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE25__GPIO_130(c) 0x208 0x208 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE25__DCU0_B4(c) 0x208 0x208 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE25__SRC_RCON14(c) 0x208 0x208 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE25__LCD25(c) 0x208 0x208 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE26__GPIO_131(c) 0x20C 0x20C 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE26__DCU0_B5(c) 0x20C 0x20C 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE26__SRC_RCON15(c) 0x20C 0x20C 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE26__LCD26(c) 0x20C 0x20C 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE27__GPIO_132(c) 0x210 0x210 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE27__DCU0_B6(c) 0x210 0x210 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE27__SRC_RCON16(c) 0x210 0x210 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE27__LCD27(c) 0x210 0x210 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE27__I2C1_SCL(c) 0x210 0x210 0x344 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTE28__GPIO_133(c) 0x214 0x214 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTE28__DCU0_B7(c) 0x214 0x214 0x000 (ALT1|c) 0 (ALT1|c) +#define MVF600_PAD_PTE28__SRC_RCON17(c) 0x214 0x214 0x000 (ALT3|c) 0 (ALT3|c) +#define MVF600_PAD_PTE28__LCD28(c) 0x214 0x214 0x000 (ALT4|c) 0 (ALT4|c) +#define MVF600_PAD_PTE28__I2C1_SDA(c) 0x214 0x214 0x348 (ALT5|c) 0 (ALT5|c) +#define MVF600_PAD_PTE28__EWM_OUT(c) 0x214 0x214 0x000 (ALT7|c) 0 (ALT7|c) +#define MVF600_PAD_PTA7__GPIO_134(c) 0x218 0x218 0x000 (ALT0|c) 0 (ALT0|c) +#define MVF600_PAD_PTA7__VIU_PIX_CLK(c) 0x218 0x218 0x3AC (ALT1|c) 0 (ALT1|c) + +#endif diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts new file mode 100644 index 0000000..e2dafa2 --- /dev/null +++ b/arch/arm/boot/dts/mvf600-twr.dts @@ -0,0 +1,80 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "mvf600.dtsi" + +/ { + model = "MVF600 Tower Board"; + compatible = "fsl,mvf600-twr", "fsl,mvf600"; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + memory { + reg = <0x80000000 0x8000000>; + }; + + clocks { + osc { + compatible = "fsl,mvf-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + + audio_clk { + compatible = "fsl,mvf-audio-ext-clk", "fixed-clock"; + clock-frequency = <24576000>; + }; + + enet_clk { + compatible = "fsl,mvf-enet-ext-clk", "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0_1>; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1_1>; +}; + + +&qspi0 { /* QuadSPI0 */ + fsl,spi-num-chipselects = <1>; + fsl,spi-flash-chipselects = <0>; + status = "okay"; + + flash: s25fl128s at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s"; + spi-max-frequency = <20000000>; + reg = <0>; + linux,modalias = "m25p80"; + modal = "s25fl128s"; + partition at 0 { + label = "s25fl128s"; + reg = <0x0 0x1000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi new file mode 100644 index 0000000..ca25f80 --- /dev/null +++ b/arch/arm/boot/dts/mvf600.dtsi @@ -0,0 +1,426 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "skeleton.dtsi" +#include "mvf600-pinfunc.h" +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + + clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips0: aips-bus at 40000000 { /* AIPS0 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + reg = <0x40000000 0x70000>; + ranges; + + mscm: mscm at 40001000 { + compatible = "fsl,mvf-mscm"; + reg = <0x40001000 0x1000>; + }; + + intc: interrupt-controller at 40002000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x40003000 0x1000>, + <0x40002100 0x100>; + }; + + L2: l2-cache at 40006000 { + compatible = "arm,pl310-cache"; + reg = <0x40006000 0x1000>; + interrupts = <0 6 0x04>; + cache-unified; + cache-level = <2>; + }; + + uart0: serial at 40027000 { /* UART0 */ + compatible = "fsl,mvf-uart"; + reg = <0x40027000 0x1000>; + interrupts = <0 61 0x00>; + clocks = <&clks 39>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart1: serial at 40028000 { /* UART1 */ + compatible = "fsl,mvf-uart"; + reg = <0x40028000 0x1000>; + interrupts = <0 62 0x04>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart2: serial at 40029000 { /* UART2 */ + compatible = "fsl,mvf-uart"; + reg = <0x40029000 0x1000>; + interrupts = <0 63 0x04>; + clocks = <&clks 41>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart3: serial at 4002a000 { /* UART3 */ + compatible = "fsl,mvf-uart"; + reg = <0x4002a000 0x1000>; + interrupts = <0 64 0x04>; + clocks = <&clks 42>; + clock-names = "ipg"; + status = "disabled"; + }; + + pit:pit at 40037000 { + compatible = "fsl,mvf-pit"; + reg = <0x40037000 0x1000>; + interrupts = <0 39 0x04>; + clock-names = "pit"; + clocks = <&clks 45>; + }; + + wdog at 4003e000 { + compatible = "fsl,mvf-wdt"; + reg = <0x4003e000 0x1000>; + clock-names = "wdog"; + clocks = <&clks 76>; + }; + + qspi0: quadspi at 40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mvf-qspi"; + reg = <0x40044000 0x1000>; + interrupts = <0 24 0x04>; + status = "disabled"; + }; + + iomuxc: iomuxc at 40048000 { + compatible = "fsl,mvf-iomuxc"; + reg = <0x40048000 0x1000>; + #gpio-range-cells = <2>; + + /* functions and groups pins */ + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp_1 { + fsl,pins = < + MVF600_PAD_PTA24__ESDHC1_CLK(0x31ef) + MVF600_PAD_PTA25__ESDHC1_CMD(0x31ef) + MVF600_PAD_PTA26__ESDHC1_DAT0(0x31ef) + MVF600_PAD_PTA27__ESDHC1_DAT1(0x31ef) + MVF600_PAD_PTA28__ESDHC1_DATA2(0x31ef) + MVF600_PAD_PTA29__ESDHC1_DAT3(0x31ef) + MVF600_PAD_PTA7__GPIO_134(0x219d) + >; + }; + }; + + i2c0 { + pinctrl_i2c0_1: i2c0grp_1 { + fsl,pins = < + MVF600_PAD_PTB14__I2C0_SCL(0x30d3) + MVF600_PAD_PTB15__I2C0_SDA(0x30d3) + >; + }; + }; + + dspi0 { + pinctrl_dspi0_1: dspi0grp_1 { + fsl,pins = < + MVF600_PAD_PTB19__DSPI0_CS0(0x1182) + MVF600_PAD_PTB20__DSPI0_SIN(0x1181) + MVF600_PAD_PTB21__DSPI0_SOUT(0x1182) + MVF600_PAD_PTB22__DSPI0_SCK(0x1182) + >; + }; + }; + + fec0 { + pinctrl_fec0_1: fec0grp_1 { + fsl,pins = < + MVF600_PAD_PTA6__RMII_CLKIN(0x30d1) + MVF600_PAD_PTC0__ENET_RMII0_MDC(0x30d3) + MVF600_PAD_PTC1__ENET_RMII0_MDIO(0x30d1) + MVF600_PAD_PTC2__ENET_RMII0_CRS(0x30d1) + MVF600_PAD_PTC3__ENET_RMII0_RXD1(0x30d1) + MVF600_PAD_PTC4__ENET_RMII0_RXD0(0x30d1) + MVF600_PAD_PTC5__ENET_RMII0_RXER(0x30d1) + MVF600_PAD_PTC6__ENET_RMII0_TXD1(0x30d2) + MVF600_PAD_PTC7__ENET_RMII0_TXD0(0x30d2) + MVF600_PAD_PTC8__ENET_RMII0_TXEN(0x30d2) + >; + }; + }; + + fec1 { + pinctrl_fec1_1: fec1grp_1 { + fsl,pins = < + MVF600_PAD_PTC9__ENET_RMII1_MDC(0x30d2) + MVF600_PAD_PTC10__ENET_RMII1_MDIO(0x30d3) + MVF600_PAD_PTC11__ENET_RMII1_CRS(0x30d1) + MVF600_PAD_PTC12__ENET_RMII_RXD1(0x30d1) + MVF600_PAD_PTC13__ENET_RMII1_RXD0(0x30d1) + MVF600_PAD_PTC14__ENET_RMII1_RXER(0x30d1) + MVF600_PAD_PTC15__ENET_RMII1_TXD1(0x30d2) + MVF600_PAD_PTC16__ENET_RMII1_TXD0(0x30d2) + MVF600_PAD_PTC17__ENET_RMII1_TXEN(0x30d2) + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MVF600_PAD_PTA16__SAI2_TX_BCLK(0x02ed) + MVF600_PAD_PTA18__SAI2_TX_DATA(0x02ee) + MVF600_PAD_PTA19__SAI2_TX_SYNC(0x02ed) + MVF600_PAD_PTA21__SAI2_RX_BCLK(0x02ed) + MVF600_PAD_PTA22__SAI2_RX_DATA(0x02ed) + MVF600_PAD_PTA23__SAI2_RX_SYNC(0x02ed) + MVF600_PAD_PTB18__EXT_AUDIO_MCLK(0x02ed) + >; + }; + }; + + dcu0 { + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + MVF600_PAD_PTB8__GPIO_30(0x42) + MVF600_PAD_PTE0__DCU0_HSYNC(0x42) + MVF600_PAD_PTE1__DCU0_VSYNC(0x42) + MVF600_PAD_PTE2__DCU0_PCLK(0x42) + MVF600_PAD_PTE4__DCU0_DE(0x42) + MVF600_PAD_PTE5__DCU0_R0(0x42) + MVF600_PAD_PTE6__DCU0_R1(0x42) + MVF600_PAD_PTE7__DCU0_R2(0x42) + MVF600_PAD_PTE8__DCU0_R3(0x42) + MVF600_PAD_PTE9__DCU0_R4(0x42) + MVF600_PAD_PTE10__DCU0_R5(0x42) + MVF600_PAD_PTE11__DCU0_R6(0x42) + MVF600_PAD_PTE12__DCU0_R7(0x42) + MVF600_PAD_PTE13__DCU0_G0(0x42) + MVF600_PAD_PTE14__DCU0_G1(0x42) + MVF600_PAD_PTE15__DCU0_G2(0x42) + MVF600_PAD_PTE16__DCU0_G3(0x42) + MVF600_PAD_PTE17__DCU0_G4(0x42) + MVF600_PAD_PTE18__DCU0_G5(0x42) + MVF600_PAD_PTE19__DCU0_G6(0x42) + MVF600_PAD_PTE20__DCU0_G7(0x42) + MVF600_PAD_PTE21__DCU0_B0(0x42) + MVF600_PAD_PTE22__DCU0_B1(0x42) + MVF600_PAD_PTE23__DCU0_B2(0x42) + MVF600_PAD_PTE24__DCU0_B3(0x42) + MVF600_PAD_PTE25__DCU0_B4(0x42) + MVF600_PAD_PTE26__DCU0_B5(0x42) + MVF600_PAD_PTE27__DCU0_B6(0x42) + MVF600_PAD_PTE28__DCU0_B7(0x42) + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp_1 { + fsl,pins = < + MVF600_PAD_PTB4__UART1_TX(0x21a2) + MVF600_PAD_PTB5__UART1_RX(0x21a1) + >; + }; + }; + + usbvbus { + pinctrl_usbvbus_1: usbvbusgrp_1 { + fsl,pins = < + MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c) + MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c) + >; + }; + }; + + pwm0 { + pinctrl_pwm0_1: pwm0grp_1 { + fsl,pins = < + MVF600_PAD_PTB0__FTM0_CH0(0x1582) + MVF600_PAD_PTB1__FTM0_CH1(0x1582) + MVF600_PAD_PTB2__FTM0_CH2(0x1582) + MVF600_PAD_PTB3__FTM0_CH3(0x1582) + MVF600_PAD_PTB6__FTM0_CH6(0x1582) + MVF600_PAD_PTB7__FTM0_CH7(0x1582) + >; + }; + }; + + qspi0 { + pinctrl_qspi0_1: qspi0grp_1 { + fsl,pins = < + MVF600_PAD_PTD0__QSPI0_A_QSCK(0x307b) + MVF600_PAD_PTD1__QSPI0_A_CS0(0x307f) + MVF600_PAD_PTD2__QSPI0_A_DATA3(0x3073) + MVF600_PAD_PTD3__QSPI0_A_DATA2(0x3073) + MVF600_PAD_PTD4__QSPI0_A_DATA1(0x3073) + MVF600_PAD_PTD5__QSPI0_A_DATA0(0x307b) + MVF600_PAD_PTD7__QSPI0_B_QSCK(0x307b) + MVF600_PAD_PTD8__QSPI0_B_CS0(0x307f) + MVF600_PAD_PTD9__QSPI0_B_DATA3(0x3073) + MVF600_PAD_PTD10__QSPI0_B_DATA2(0x3073) + MVF600_PAD_PTD11__QSPI0_B_DATA1(0x3073) + MVF600_PAD_PTD12__QSPI0_B_DATA0(0x307b) + >; + }; + }; + + touchscreen0 { + pinctrl_ts0_1: ts0grp_1 { + fsl,pins = < + MVF600_PAD_PTA31__GPIO_21(0x219d) + >; + }; + }; + + }; + + gpio1: gpio at 40049000 { + compatible = "fsl,mvf-gpio"; + reg = <0x40049000 0x1000 0x400ff000 0x40>; + interrupts = <0 107 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32>; + }; + + gpio2: gpio at 4004a000 { + compatible = "fsl,mvf-gpio"; + reg = <0x4004a000 0x1000 0x400ff040 0x40>; + interrupts = <0 108 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 32 32>; + }; + + gpio3: gpio at 4004b000 { + compatible = "fsl,mvf-gpio"; + reg = <0x4004b000 0x1000 0x400ff080 0x40>; + interrupts = <0 109 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 64 32>; + }; + + gpio4: gpio at 4004c000 { + compatible = "fsl,mvf-gpio"; + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; + interrupts = <0 110 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 96 32>; + }; + + gpio5: gpio at 4004d000 { + compatible = "fsl,mvf-gpio"; + reg = <0x4004d000 0x1000 0x400ff100 0x40>; + interrupts = <0 111 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 128 7>; + }; + + anatop at 40050000 { + compatible = "fsl,mvf-anatop"; + reg = <0x40050000 0x1000>; + }; + + clks: ccm at 4006b000 { + compatible = "fsl,mvf-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + }; + + }; + + aips1: aips-bus at 40080000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40080000 0x80000>; + ranges; + + uart4: serial at 400a9000 { /* UART4 */ + compatible = "fsl,mvf-uart"; + reg = <0x400a9000 0x1000>; + interrupts = <0 65 0x04>; + clocks = <&clks 43>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart5: serial at 400aa000 { /* UART5 */ + compatible = "fsl,mvf-uart"; + reg = <0x400aa000 0x1000>; + interrupts = <0 66 0x04>; + clocks = <&clks 44>; + clock-names = "ipg"; + status = "disabled"; + }; + + fec0: ethernet at 400d0000 { + compatible = "fsl,mvf-fec"; + reg = <0x400d0000 0x1000>; + interrupts = <0 78 0x04>; + clocks = <&clks 69>, <&clks 69>, <&clks 69>; + clock-names = "ipg", "ahb", "ptp"; + }; + + fec1: ethernet at 400d1000 { + compatible = "fsl,mvf-fec"; + reg = <0x400d1000 0x1000>; + interrupts = <0 79 0x04>; + clocks = <&clks 69>, <&clks 69>, <&clks 69>; + clock-names = "ipg", "ahb", "ptp"; + }; + + }; + }; +}; -- 1.8.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid 2013-05-02 7:38 ` [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid Jingchang Lu @ 2013-05-02 8:56 ` Sascha Hauer 2013-05-06 2:38 ` Shawn Guo 1 sibling, 0 replies; 13+ messages in thread From: Sascha Hauer @ 2013-05-02 8:56 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 02, 2013 at 03:38:05PM +0800, Jingchang Lu wrote: > This patch adds basic device tree source for Freescale > Vybrid Family MVF600 platform and Tower development board. > > Signed-off-by: Xiaochun Li <b41219@freescale.com> > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > V2: > Add pinctrl support based on IMX new pinctrl framework > > arch/arm/boot/dts/Makefile | 3 +- > arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/mvf600-twr.dts | 80 ++++ > arch/arm/boot/dts/mvf600.dtsi | 426 +++++++++++++++++++ > 4 files changed, 1324 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h > create mode 100644 arch/arm/boot/dts/mvf600-twr.dts > create mode 100644 arch/arm/boot/dts/mvf600.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 8fd41b3..6402f21 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ > imx6q-sabreauto.dtb \ > imx6q-sabrelite.dtb \ > imx6q-sabresd.dtb \ > - imx6q-sbc6x.dtb > + imx6q-sbc6x.dtb \ > + mvf600-twr.dtb > dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ > imx23-olinuxino.dtb \ > imx23-stmp378x_devb.dtb \ > diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h > new file mode 100644 > index 0000000..9fbc7a9 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600-pinfunc.h > @@ -0,0 +1,816 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#ifndef __DTS_MVF600_PINFUNC_H > +#define __DTS_MVF600_PINFUNC_H > + > +/* > + * Macro definations for MVF600 pin functions s/definations/definitions/ > diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts Make this a separate patch please. It's board specific whereas the rest is SoC specific. > + aips1: aips-bus at 40080000 { /* AIPS1 */ > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x40080000 0x80000>; > + ranges; > + > + uart4: serial at 400a9000 { /* UART4 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x400a9000 0x1000>; > + interrupts = <0 65 0x04>; > + clocks = <&clks 43>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart5: serial at 400aa000 { /* UART5 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x400aa000 0x1000>; > + interrupts = <0 66 0x04>; > + clocks = <&clks 44>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + fec0: ethernet at 400d0000 { > + compatible = "fsl,mvf-fec"; > + reg = <0x400d0000 0x1000>; > + interrupts = <0 78 0x04>; > + clocks = <&clks 69>, <&clks 69>, <&clks 69>; > + clock-names = "ipg", "ahb", "ptp"; status = "disabled"; > + }; > + > + fec1: ethernet at 400d1000 { > + compatible = "fsl,mvf-fec"; > + reg = <0x400d1000 0x1000>; > + interrupts = <0 79 0x04>; > + clocks = <&clks 69>, <&clks 69>, <&clks 69>; > + clock-names = "ipg", "ahb", "ptp"; status = "disabled"; Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid 2013-05-02 7:38 ` [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid Jingchang Lu 2013-05-02 8:56 ` Sascha Hauer @ 2013-05-06 2:38 ` Shawn Guo 1 sibling, 0 replies; 13+ messages in thread From: Shawn Guo @ 2013-05-06 2:38 UTC (permalink / raw) To: linux-arm-kernel Generally, we use prefix "ARM: dts: ..." for arch/arm/dts and "ARM: imx: ..." for arch/arm/mach-imx changes. On Thu, May 02, 2013 at 03:38:05PM +0800, Jingchang Lu wrote: > This patch adds basic device tree source for Freescale > Vybrid Family MVF600 platform and Tower development board. > > Signed-off-by: Xiaochun Li <b41219@freescale.com> > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > V2: > Add pinctrl support based on IMX new pinctrl framework > > arch/arm/boot/dts/Makefile | 3 +- > arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/mvf600-twr.dts | 80 ++++ > arch/arm/boot/dts/mvf600.dtsi | 426 +++++++++++++++++++ > 4 files changed, 1324 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h > create mode 100644 arch/arm/boot/dts/mvf600-twr.dts > create mode 100644 arch/arm/boot/dts/mvf600.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 8fd41b3..6402f21 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ > imx6q-sabreauto.dtb \ > imx6q-sabrelite.dtb \ > imx6q-sabresd.dtb \ > - imx6q-sbc6x.dtb > + imx6q-sbc6x.dtb \ > + mvf600-twr.dtb > dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ > imx23-olinuxino.dtb \ > imx23-stmp378x_devb.dtb \ > diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h > new file mode 100644 > index 0000000..9fbc7a9 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600-pinfunc.h > @@ -0,0 +1,816 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#ifndef __DTS_MVF600_PINFUNC_H > +#define __DTS_MVF600_PINFUNC_H > + > +/* > + * Macro definations for MVF600 pin functions > + * > + * On Vybrid,pin's mux mode and pad control are in one 32-bit register. > + * mux mode bits occupy bit[20:22] and pad config bits occupy bit[[0:15]. > + * So the config word is a combination of mux mode and control config value. > + * imx common pinctrl driver requires a tuple of six elements to > + * describe a pin. The tuple for MVF600 is as below: > + * <mux_reg conf_reg input_reg mux_mode|conf_val input_val mux_mode|conf_val> As I commented on the pinctrl driver, I prefer to define mvf600 pinfunc ID as <mux_reg input_reg mux_mode input_val> and have pinctrl driver handle the differences between mvf600 and imx. > + */ ... > diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts > new file mode 100644 > index 0000000..e2dafa2 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600-twr.dts > @@ -0,0 +1,80 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +/dts-v1/; > +#include "mvf600.dtsi" > + > +/ { > + model = "MVF600 Tower Board"; > + compatible = "fsl,mvf600-twr", "fsl,mvf600"; > + > + chosen { > + bootargs = "console=ttymxc1,115200"; > + }; > + > + memory { > + reg = <0x80000000 0x8000000>; > + }; > + > + clocks { > + osc { > + compatible = "fsl,mvf-osc", "fixed-clock"; Please drop the custom compatible for these fixed rate clocks, as we will use common of_clk_init() to register them. > + clock-frequency = <24000000>; > + }; > + > + audio_clk { > + compatible = "fsl,mvf-audio-ext-clk", "fixed-clock"; > + clock-frequency = <24576000>; > + }; > + > + enet_clk { > + compatible = "fsl,mvf-enet-ext-clk", "fixed-clock"; > + clock-frequency = <50000000>; > + }; > + }; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1_1>; > + status = "okay"; > +}; > + > +&fec0 { > + phy-mode = "rmii"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec0_1>; > +}; Please sort the nodes in alphabet order of the labels, something like the below. &fec0 { ... }; &fec1 { ... }; &qspi00 { ... }; &uart1 { ... }; > + > +&fec1 { > + phy-mode = "rmii"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1_1>; > +}; > + > + > +&qspi0 { /* QuadSPI0 */ > + fsl,spi-num-chipselects = <1>; > + fsl,spi-flash-chipselects = <0>; > + status = "okay"; > + > + flash: s25fl128s at 0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "spansion,s25fl128s"; > + spi-max-frequency = <20000000>; > + reg = <0>; > + linux,modalias = "m25p80"; > + modal = "s25fl128s"; > + partition at 0 { > + label = "s25fl128s"; > + reg = <0x0 0x1000000>; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi > new file mode 100644 > index 0000000..ca25f80 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600.dtsi > @@ -0,0 +1,426 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include "skeleton.dtsi" > +#include "mvf600-pinfunc.h" Put a blank line here. > +/ { > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + }; > + > + Remove one blank line here. > + clocks { > + #address-cells = <1>; > + #size-cells = <0>; If like imx that "osc" is a clock which is defined by SoC, the clock should be put here rather than board dts. > + }; > + > + One blank line is enough. > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&intc>; > + ranges; > + > + aips0: aips-bus at 40000000 { /* AIPS0 */ With the label aips0 in front of, the comment "/* AIPS0 */" can just be saved. > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + reg = <0x40000000 0x70000>; > + ranges; > + > + mscm: mscm at 40001000 { > + compatible = "fsl,mvf-mscm"; We generally specify a particular hardware version by using given SoC name in compatible. So in your case, "fsl,mvf600-mscm" is the one we want to use. > + reg = <0x40001000 0x1000>; > + }; > + > + intc: interrupt-controller at 40002000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-controller; > + reg = <0x40003000 0x1000>, > + <0x40002100 0x100>; > + }; > + > + L2: l2-cache at 40006000 { > + compatible = "arm,pl310-cache"; > + reg = <0x40006000 0x1000>; > + interrupts = <0 6 0x04>; > + cache-unified; > + cache-level = <2>; You may want the similar change as the patch below adds for imx6? https://patchwork.kernel.org/patch/2491311/ > + }; > + > + uart0: serial at 40027000 { /* UART0 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x40027000 0x1000>; > + interrupts = <0 61 0x00>; > + clocks = <&clks 39>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart1: serial at 40028000 { /* UART1 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x40028000 0x1000>; > + interrupts = <0 62 0x04>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart2: serial at 40029000 { /* UART2 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x40029000 0x1000>; > + interrupts = <0 63 0x04>; > + clocks = <&clks 41>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart3: serial at 4002a000 { /* UART3 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x4002a000 0x1000>; > + interrupts = <0 64 0x04>; > + clocks = <&clks 42>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + pit:pit at 40037000 { > + compatible = "fsl,mvf-pit"; > + reg = <0x40037000 0x1000>; > + interrupts = <0 39 0x04>; > + clock-names = "pit"; > + clocks = <&clks 45>; > + }; > + > + wdog at 4003e000 { > + compatible = "fsl,mvf-wdt"; > + reg = <0x4003e000 0x1000>; > + clock-names = "wdog"; > + clocks = <&clks 76>; > + }; > + > + qspi0: quadspi at 40044000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,mvf-qspi"; > + reg = <0x40044000 0x1000>; > + interrupts = <0 24 0x04>; > + status = "disabled"; > + }; > + > + iomuxc: iomuxc at 40048000 { > + compatible = "fsl,mvf-iomuxc"; > + reg = <0x40048000 0x1000>; > + #gpio-range-cells = <2>; > + > + /* functions and groups pins */ > + esdhc1 { > + pinctrl_esdhc1_1: esdhc1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA24__ESDHC1_CLK(0x31ef) > + MVF600_PAD_PTA25__ESDHC1_CMD(0x31ef) > + MVF600_PAD_PTA26__ESDHC1_DAT0(0x31ef) > + MVF600_PAD_PTA27__ESDHC1_DAT1(0x31ef) > + MVF600_PAD_PTA28__ESDHC1_DATA2(0x31ef) > + MVF600_PAD_PTA29__ESDHC1_DAT3(0x31ef) > + MVF600_PAD_PTA7__GPIO_134(0x219d) > + >; > + }; > + }; Please sort all these iomuxc sub-nodes in alphabet sort of node name, so that the new pinctrl entries can easily find their places. Shawn > + > + i2c0 { > + pinctrl_i2c0_1: i2c0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB14__I2C0_SCL(0x30d3) > + MVF600_PAD_PTB15__I2C0_SDA(0x30d3) > + >; > + }; > + }; > + > + dspi0 { > + pinctrl_dspi0_1: dspi0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB19__DSPI0_CS0(0x1182) > + MVF600_PAD_PTB20__DSPI0_SIN(0x1181) > + MVF600_PAD_PTB21__DSPI0_SOUT(0x1182) > + MVF600_PAD_PTB22__DSPI0_SCK(0x1182) > + >; > + }; > + }; > + > + fec0 { > + pinctrl_fec0_1: fec0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA6__RMII_CLKIN(0x30d1) > + MVF600_PAD_PTC0__ENET_RMII0_MDC(0x30d3) > + MVF600_PAD_PTC1__ENET_RMII0_MDIO(0x30d1) > + MVF600_PAD_PTC2__ENET_RMII0_CRS(0x30d1) > + MVF600_PAD_PTC3__ENET_RMII0_RXD1(0x30d1) > + MVF600_PAD_PTC4__ENET_RMII0_RXD0(0x30d1) > + MVF600_PAD_PTC5__ENET_RMII0_RXER(0x30d1) > + MVF600_PAD_PTC6__ENET_RMII0_TXD1(0x30d2) > + MVF600_PAD_PTC7__ENET_RMII0_TXD0(0x30d2) > + MVF600_PAD_PTC8__ENET_RMII0_TXEN(0x30d2) > + >; > + }; > + }; > + > + fec1 { > + pinctrl_fec1_1: fec1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTC9__ENET_RMII1_MDC(0x30d2) > + MVF600_PAD_PTC10__ENET_RMII1_MDIO(0x30d3) > + MVF600_PAD_PTC11__ENET_RMII1_CRS(0x30d1) > + MVF600_PAD_PTC12__ENET_RMII_RXD1(0x30d1) > + MVF600_PAD_PTC13__ENET_RMII1_RXD0(0x30d1) > + MVF600_PAD_PTC14__ENET_RMII1_RXER(0x30d1) > + MVF600_PAD_PTC15__ENET_RMII1_TXD1(0x30d2) > + MVF600_PAD_PTC16__ENET_RMII1_TXD0(0x30d2) > + MVF600_PAD_PTC17__ENET_RMII1_TXEN(0x30d2) > + >; > + }; > + }; > + > + sai2 { > + pinctrl_sai2_1: sai2grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA16__SAI2_TX_BCLK(0x02ed) > + MVF600_PAD_PTA18__SAI2_TX_DATA(0x02ee) > + MVF600_PAD_PTA19__SAI2_TX_SYNC(0x02ed) > + MVF600_PAD_PTA21__SAI2_RX_BCLK(0x02ed) > + MVF600_PAD_PTA22__SAI2_RX_DATA(0x02ed) > + MVF600_PAD_PTA23__SAI2_RX_SYNC(0x02ed) > + MVF600_PAD_PTB18__EXT_AUDIO_MCLK(0x02ed) > + >; > + }; > + }; > + > + dcu0 { > + pinctrl_dcu0_1: dcu0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB8__GPIO_30(0x42) > + MVF600_PAD_PTE0__DCU0_HSYNC(0x42) > + MVF600_PAD_PTE1__DCU0_VSYNC(0x42) > + MVF600_PAD_PTE2__DCU0_PCLK(0x42) > + MVF600_PAD_PTE4__DCU0_DE(0x42) > + MVF600_PAD_PTE5__DCU0_R0(0x42) > + MVF600_PAD_PTE6__DCU0_R1(0x42) > + MVF600_PAD_PTE7__DCU0_R2(0x42) > + MVF600_PAD_PTE8__DCU0_R3(0x42) > + MVF600_PAD_PTE9__DCU0_R4(0x42) > + MVF600_PAD_PTE10__DCU0_R5(0x42) > + MVF600_PAD_PTE11__DCU0_R6(0x42) > + MVF600_PAD_PTE12__DCU0_R7(0x42) > + MVF600_PAD_PTE13__DCU0_G0(0x42) > + MVF600_PAD_PTE14__DCU0_G1(0x42) > + MVF600_PAD_PTE15__DCU0_G2(0x42) > + MVF600_PAD_PTE16__DCU0_G3(0x42) > + MVF600_PAD_PTE17__DCU0_G4(0x42) > + MVF600_PAD_PTE18__DCU0_G5(0x42) > + MVF600_PAD_PTE19__DCU0_G6(0x42) > + MVF600_PAD_PTE20__DCU0_G7(0x42) > + MVF600_PAD_PTE21__DCU0_B0(0x42) > + MVF600_PAD_PTE22__DCU0_B1(0x42) > + MVF600_PAD_PTE23__DCU0_B2(0x42) > + MVF600_PAD_PTE24__DCU0_B3(0x42) > + MVF600_PAD_PTE25__DCU0_B4(0x42) > + MVF600_PAD_PTE26__DCU0_B5(0x42) > + MVF600_PAD_PTE27__DCU0_B6(0x42) > + MVF600_PAD_PTE28__DCU0_B7(0x42) > + >; > + }; > + }; > + > + uart1 { > + pinctrl_uart1_1: uart1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB4__UART1_TX(0x21a2) > + MVF600_PAD_PTB5__UART1_RX(0x21a1) > + >; > + }; > + }; > + > + usbvbus { > + pinctrl_usbvbus_1: usbvbusgrp_1 { > + fsl,pins = < > + MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c) > + MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c) > + >; > + }; > + }; > + > + pwm0 { > + pinctrl_pwm0_1: pwm0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB0__FTM0_CH0(0x1582) > + MVF600_PAD_PTB1__FTM0_CH1(0x1582) > + MVF600_PAD_PTB2__FTM0_CH2(0x1582) > + MVF600_PAD_PTB3__FTM0_CH3(0x1582) > + MVF600_PAD_PTB6__FTM0_CH6(0x1582) > + MVF600_PAD_PTB7__FTM0_CH7(0x1582) > + >; > + }; > + }; > + > + qspi0 { > + pinctrl_qspi0_1: qspi0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTD0__QSPI0_A_QSCK(0x307b) > + MVF600_PAD_PTD1__QSPI0_A_CS0(0x307f) > + MVF600_PAD_PTD2__QSPI0_A_DATA3(0x3073) > + MVF600_PAD_PTD3__QSPI0_A_DATA2(0x3073) > + MVF600_PAD_PTD4__QSPI0_A_DATA1(0x3073) > + MVF600_PAD_PTD5__QSPI0_A_DATA0(0x307b) > + MVF600_PAD_PTD7__QSPI0_B_QSCK(0x307b) > + MVF600_PAD_PTD8__QSPI0_B_CS0(0x307f) > + MVF600_PAD_PTD9__QSPI0_B_DATA3(0x3073) > + MVF600_PAD_PTD10__QSPI0_B_DATA2(0x3073) > + MVF600_PAD_PTD11__QSPI0_B_DATA1(0x3073) > + MVF600_PAD_PTD12__QSPI0_B_DATA0(0x307b) > + >; > + }; > + }; > + > + touchscreen0 { > + pinctrl_ts0_1: ts0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA31__GPIO_21(0x219d) > + >; > + }; > + }; > + > + }; > + > + gpio1: gpio at 40049000 { > + compatible = "fsl,mvf-gpio"; > + reg = <0x40049000 0x1000 0x400ff000 0x40>; > + interrupts = <0 107 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 32>; > + }; > + > + gpio2: gpio at 4004a000 { > + compatible = "fsl,mvf-gpio"; > + reg = <0x4004a000 0x1000 0x400ff040 0x40>; > + interrupts = <0 108 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 32 32>; > + }; > + > + gpio3: gpio at 4004b000 { > + compatible = "fsl,mvf-gpio"; > + reg = <0x4004b000 0x1000 0x400ff080 0x40>; > + interrupts = <0 109 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 64 32>; > + }; > + > + gpio4: gpio at 4004c000 { > + compatible = "fsl,mvf-gpio"; > + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; > + interrupts = <0 110 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 96 32>; > + }; > + > + gpio5: gpio at 4004d000 { > + compatible = "fsl,mvf-gpio"; > + reg = <0x4004d000 0x1000 0x400ff100 0x40>; > + interrupts = <0 111 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 128 7>; > + }; > + > + anatop at 40050000 { > + compatible = "fsl,mvf-anatop"; > + reg = <0x40050000 0x1000>; > + }; > + > + clks: ccm at 4006b000 { > + compatible = "fsl,mvf-ccm"; > + reg = <0x4006b000 0x1000>; > + #clock-cells = <1>; > + }; > + > + }; > + > + aips1: aips-bus at 40080000 { /* AIPS1 */ > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x40080000 0x80000>; > + ranges; > + > + uart4: serial at 400a9000 { /* UART4 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x400a9000 0x1000>; > + interrupts = <0 65 0x04>; > + clocks = <&clks 43>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart5: serial at 400aa000 { /* UART5 */ > + compatible = "fsl,mvf-uart"; > + reg = <0x400aa000 0x1000>; > + interrupts = <0 66 0x04>; > + clocks = <&clks 44>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + fec0: ethernet at 400d0000 { > + compatible = "fsl,mvf-fec"; > + reg = <0x400d0000 0x1000>; > + interrupts = <0 78 0x04>; > + clocks = <&clks 69>, <&clks 69>, <&clks 69>; > + clock-names = "ipg", "ahb", "ptp"; > + }; > + > + fec1: ethernet at 400d1000 { > + compatible = "fsl,mvf-fec"; > + reg = <0x400d1000 0x1000>; > + interrupts = <0 79 0x04>; > + clocks = <&clks 69>, <&clks 69>, <&clks 69>; > + clock-names = "ipg", "ahb", "ptp"; > + }; > + > + }; > + }; > +}; > -- > 1.8.0 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board. 2013-05-02 7:38 [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Jingchang Lu 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu 2013-05-02 7:38 ` [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid Jingchang Lu @ 2013-05-03 2:40 ` Shawn Guo 2 siblings, 0 replies; 13+ messages in thread From: Shawn Guo @ 2013-05-03 2:40 UTC (permalink / raw) To: linux-arm-kernel I don't know how it gets wrong, but the Subject line apparently contains some message that should be put in the email body. Shawn On Thu, May 02, 2013 at 03:38:03PM +0800, Jingchang Lu wrote: > Documentation/devicetree/bindings/clock/mvf600-clock.txt | 180 ++++++++ > arch/arm/boot/dts/Makefile | 3 +- > arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/mvf600-twr.dts | 80 ++++ > arch/arm/boot/dts/mvf600.dtsi | 426 ++++++++++++++++++ > arch/arm/mach-imx/Kconfig | 15 + > arch/arm/mach-imx/Makefile | 3 + > arch/arm/mach-imx/clk-mvf.c | 406 +++++++++++++++++ > arch/arm/mach-imx/common.h | 1 + > arch/arm/mach-imx/mach-mvf600.c | 118 +++++ > arch/arm/mach-imx/pit.c | 244 +++++++++++ > 11 files changed, 2291 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt > create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h > create mode 100644 arch/arm/boot/dts/mvf600-twr.dts > create mode 100644 arch/arm/boot/dts/mvf600.dtsi > create mode 100644 arch/arm/mach-imx/clk-mvf.c > create mode 100644 arch/arm/mach-imx/mach-mvf600.c > create mode 100644 arch/arm/mach-imx/pit.c > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2013-05-08 18:03 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-02 7:38 [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Jingchang Lu 2013-05-02 7:38 ` [PATCH V2 1/2] ARM/MVF600: add Vybrid Family platform support Jingchang Lu 2013-05-02 8:52 ` Sascha Hauer 2013-05-02 9:20 ` Lu Jingchang-B35083 2013-05-02 16:53 ` Mike Turquette 2013-05-03 7:41 ` Shawn Guo 2013-05-08 7:26 ` Lu Jingchang-B35083 2013-05-08 14:38 ` Shawn Guo 2013-05-08 18:03 ` Russell King - ARM Linux 2013-05-02 7:38 ` [PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid Jingchang Lu 2013-05-02 8:56 ` Sascha Hauer 2013-05-06 2:38 ` Shawn Guo 2013-05-03 2:40 ` [PATCH V2 0/2] ARM/MVF600: add Freescale Vybrid Family platform and development board support This Vybird MVF600 family is a heterogeneous dual-core eMPU family combining the ARM Cortex-A5 and Corte-M4 cores. This SOC still shares some IPs with Iscale Vybrid Family SOC and Vybrid Tower development board Shawn Guo
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