From: Jason Cooper <jason@lakedaemon.net>
To: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
Arnd Bergmann <arnd@arndb.de>, Maen Suleiman <maen@marvell.com>,
linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org,
Thierry Reding <thierry.reding@avionic-design.de>,
Rob Herring <rob.herring@calxeda.com>,
Grant Likely <grant.likely@secretlab.ca>,
Olof Johansson <olof@lixom.net>,
Gregory Clement <gregory.clement@free-electrons.com>,
Tawfik Bayouk <tawfik@marvell.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-arm-kernel@lists.infradead.org,
Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Subject: Re: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
Date: Thu, 16 May 2013 11:40:31 -0400 [thread overview]
Message-ID: <20130516154031.GF6563@titan.lakedaemon.net> (raw)
In-Reply-To: <20130516093312.GB2459@localhost>
On Thu, May 16, 2013 at 06:33:14AM -0300, Ezequiel Garcia wrote:
> On Wed, May 15, 2013 at 03:25:21PM +0200, Thomas Petazzoni wrote:
> [..]
> > +
> > +static int __init mvebu_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct mvebu_pcie *pcie;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct of_pci_range range;
> > + struct of_pci_range_parser parser;
> > + struct device_node *child;
> > + int i, ret;
> > +
> > + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
> > + GFP_KERNEL);
> > + if (!pcie)
> > + return -ENOMEM;
> > +
> > + pcie->pdev = pdev;
> > +
> > + if (of_pci_range_parser_init(&parser, np))
> > + return -EINVAL;
> > +
> > + /* Get the I/O and memory ranges from DT */
> > + for_each_of_pci_range(&parser, &range) {
> > + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
> > + if (restype == IORESOURCE_IO) {
> > + of_pci_range_to_resource(&range, np, &pcie->io);
> > + of_pci_range_to_resource(&range, np, &pcie->realio);
> > + pcie->io.name = "I/O";
> > + pcie->realio.start = max_t(resource_size_t,
> > + PCIBIOS_MIN_IO,
> > + range.pci_addr);
> > + pcie->realio.end = min_t(resource_size_t,
> > + IO_SPACE_LIMIT,
> > + range.pci_addr + range.size);
> > + }
> > + if (restype == IORESOURCE_MEM) {
> > + of_pci_range_to_resource(&range, np, &pcie->mem);
> > + pcie->mem.name = "MEM";
> > + }
> > + }
> > +
> > + /* Get the bus range */
> > + ret = of_pci_parse_bus_range(np, &pcie->busn);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + if (!of_device_is_available(child))
> > + continue;
> > + pcie->nports++;
> > + }
> > +
> > + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
> > + sizeof(struct mvebu_pcie_port),
> > + GFP_KERNEL);
> > + if (!pcie->ports)
> > + return -ENOMEM;
> > +
> > + i = 0;
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + struct mvebu_pcie_port *port = &pcie->ports[i];
> > +
> > + if (!of_device_is_available(child))
> > + continue;
> > +
> > + port->pcie = pcie;
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-port",
> > + &port->port)) {
> > + dev_warn(&pdev->dev,
> > + "ignoring PCIe DT node, missing pcie-port property\n");
> > + continue;
> > + }
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-lane",
> > + &port->lane))
> > + port->lane = 0;
> > +
> > + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
> > + port->port, port->lane);
> > +
> > + port->devfn = of_pci_get_devfn(child);
> > + if (port->devfn < 0)
> > + continue;
> > +
> > + port->base = mvebu_pcie_map_registers(pdev, child, port);
> > + if (!port->base) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
> > + port->port, port->lane);
> > + continue;
> > + }
> > +
> > + if (mvebu_pcie_link_up(port)) {
> > + port->haslink = 1;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
> > + port->port, port->lane);
> > + } else {
> > + port->haslink = 0;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
> > + port->port, port->lane);
> > + }
> > +
> > + port->clk = of_clk_get_by_name(child, NULL);
> > + if (!port->clk) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
> > + port->port, port->lane);
> > + iounmap(port->base);
> > + port->haslink = 0;
> > + continue;
> > + }
> > +
> > + port->dn = child;
> > +
> > + clk_prepare_enable(port->clk);
> > + spin_lock_init(&port->conf_lock);
> > +
> > + mvebu_sw_pci_bridge_init(port);
> > +
> > + i++;
> > + }
> > +
> > + mvebu_pcie_enable(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mvebu_pcie_of_match_table[] = {
> > + { .compatible = "marvell,armada-xp-pcie", },
> > + { .compatible = "marvell,armada-370-pcie", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
> > +
> > +static struct platform_driver mvebu_pcie_driver = {
> > + .driver = {
> > + .owner = THIS_MODULE,
> > + .name = "mvebu-pcie",
> > + .of_match_table =
> > + of_match_ptr(mvebu_pcie_of_match_table),
> > + },
> > +};
> > +
> > +static int mvebu_pcie_init(void)
>
> Building this showed a warning here. It seems you forgot
> to mark this one as __init.
Thomas, I'll fix this up when I pull this in, no need to resend. :)
thx,
Jason.
WARNING: multiple messages have this Message-ID (diff)
From: jason@lakedaemon.net (Jason Cooper)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
Date: Thu, 16 May 2013 11:40:31 -0400 [thread overview]
Message-ID: <20130516154031.GF6563@titan.lakedaemon.net> (raw)
In-Reply-To: <20130516093312.GB2459@localhost>
On Thu, May 16, 2013 at 06:33:14AM -0300, Ezequiel Garcia wrote:
> On Wed, May 15, 2013 at 03:25:21PM +0200, Thomas Petazzoni wrote:
> [..]
> > +
> > +static int __init mvebu_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct mvebu_pcie *pcie;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct of_pci_range range;
> > + struct of_pci_range_parser parser;
> > + struct device_node *child;
> > + int i, ret;
> > +
> > + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
> > + GFP_KERNEL);
> > + if (!pcie)
> > + return -ENOMEM;
> > +
> > + pcie->pdev = pdev;
> > +
> > + if (of_pci_range_parser_init(&parser, np))
> > + return -EINVAL;
> > +
> > + /* Get the I/O and memory ranges from DT */
> > + for_each_of_pci_range(&parser, &range) {
> > + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
> > + if (restype == IORESOURCE_IO) {
> > + of_pci_range_to_resource(&range, np, &pcie->io);
> > + of_pci_range_to_resource(&range, np, &pcie->realio);
> > + pcie->io.name = "I/O";
> > + pcie->realio.start = max_t(resource_size_t,
> > + PCIBIOS_MIN_IO,
> > + range.pci_addr);
> > + pcie->realio.end = min_t(resource_size_t,
> > + IO_SPACE_LIMIT,
> > + range.pci_addr + range.size);
> > + }
> > + if (restype == IORESOURCE_MEM) {
> > + of_pci_range_to_resource(&range, np, &pcie->mem);
> > + pcie->mem.name = "MEM";
> > + }
> > + }
> > +
> > + /* Get the bus range */
> > + ret = of_pci_parse_bus_range(np, &pcie->busn);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + if (!of_device_is_available(child))
> > + continue;
> > + pcie->nports++;
> > + }
> > +
> > + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
> > + sizeof(struct mvebu_pcie_port),
> > + GFP_KERNEL);
> > + if (!pcie->ports)
> > + return -ENOMEM;
> > +
> > + i = 0;
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + struct mvebu_pcie_port *port = &pcie->ports[i];
> > +
> > + if (!of_device_is_available(child))
> > + continue;
> > +
> > + port->pcie = pcie;
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-port",
> > + &port->port)) {
> > + dev_warn(&pdev->dev,
> > + "ignoring PCIe DT node, missing pcie-port property\n");
> > + continue;
> > + }
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-lane",
> > + &port->lane))
> > + port->lane = 0;
> > +
> > + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
> > + port->port, port->lane);
> > +
> > + port->devfn = of_pci_get_devfn(child);
> > + if (port->devfn < 0)
> > + continue;
> > +
> > + port->base = mvebu_pcie_map_registers(pdev, child, port);
> > + if (!port->base) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
> > + port->port, port->lane);
> > + continue;
> > + }
> > +
> > + if (mvebu_pcie_link_up(port)) {
> > + port->haslink = 1;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
> > + port->port, port->lane);
> > + } else {
> > + port->haslink = 0;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
> > + port->port, port->lane);
> > + }
> > +
> > + port->clk = of_clk_get_by_name(child, NULL);
> > + if (!port->clk) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
> > + port->port, port->lane);
> > + iounmap(port->base);
> > + port->haslink = 0;
> > + continue;
> > + }
> > +
> > + port->dn = child;
> > +
> > + clk_prepare_enable(port->clk);
> > + spin_lock_init(&port->conf_lock);
> > +
> > + mvebu_sw_pci_bridge_init(port);
> > +
> > + i++;
> > + }
> > +
> > + mvebu_pcie_enable(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mvebu_pcie_of_match_table[] = {
> > + { .compatible = "marvell,armada-xp-pcie", },
> > + { .compatible = "marvell,armada-370-pcie", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
> > +
> > +static struct platform_driver mvebu_pcie_driver = {
> > + .driver = {
> > + .owner = THIS_MODULE,
> > + .name = "mvebu-pcie",
> > + .of_match_table =
> > + of_match_ptr(mvebu_pcie_of_match_table),
> > + },
> > +};
> > +
> > +static int mvebu_pcie_init(void)
>
> Building this showed a warning here. It seems you forgot
> to mark this one as __init.
Thomas, I'll fix this up when I pull this in, no need to resend. :)
thx,
Jason.
WARNING: multiple messages have this Message-ID (diff)
From: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
To: Ezequiel Garcia
<ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Tawfik Bayouk <tawfik-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
Thierry Reding
<thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Maen Suleiman <maen-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Jason Gunthorpe
<jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
Subject: Re: [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems
Date: Thu, 16 May 2013 11:40:31 -0400 [thread overview]
Message-ID: <20130516154031.GF6563@titan.lakedaemon.net> (raw)
In-Reply-To: <20130516093312.GB2459@localhost>
On Thu, May 16, 2013 at 06:33:14AM -0300, Ezequiel Garcia wrote:
> On Wed, May 15, 2013 at 03:25:21PM +0200, Thomas Petazzoni wrote:
> [..]
> > +
> > +static int __init mvebu_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct mvebu_pcie *pcie;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct of_pci_range range;
> > + struct of_pci_range_parser parser;
> > + struct device_node *child;
> > + int i, ret;
> > +
> > + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
> > + GFP_KERNEL);
> > + if (!pcie)
> > + return -ENOMEM;
> > +
> > + pcie->pdev = pdev;
> > +
> > + if (of_pci_range_parser_init(&parser, np))
> > + return -EINVAL;
> > +
> > + /* Get the I/O and memory ranges from DT */
> > + for_each_of_pci_range(&parser, &range) {
> > + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
> > + if (restype == IORESOURCE_IO) {
> > + of_pci_range_to_resource(&range, np, &pcie->io);
> > + of_pci_range_to_resource(&range, np, &pcie->realio);
> > + pcie->io.name = "I/O";
> > + pcie->realio.start = max_t(resource_size_t,
> > + PCIBIOS_MIN_IO,
> > + range.pci_addr);
> > + pcie->realio.end = min_t(resource_size_t,
> > + IO_SPACE_LIMIT,
> > + range.pci_addr + range.size);
> > + }
> > + if (restype == IORESOURCE_MEM) {
> > + of_pci_range_to_resource(&range, np, &pcie->mem);
> > + pcie->mem.name = "MEM";
> > + }
> > + }
> > +
> > + /* Get the bus range */
> > + ret = of_pci_parse_bus_range(np, &pcie->busn);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + if (!of_device_is_available(child))
> > + continue;
> > + pcie->nports++;
> > + }
> > +
> > + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
> > + sizeof(struct mvebu_pcie_port),
> > + GFP_KERNEL);
> > + if (!pcie->ports)
> > + return -ENOMEM;
> > +
> > + i = 0;
> > + for_each_child_of_node(pdev->dev.of_node, child) {
> > + struct mvebu_pcie_port *port = &pcie->ports[i];
> > +
> > + if (!of_device_is_available(child))
> > + continue;
> > +
> > + port->pcie = pcie;
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-port",
> > + &port->port)) {
> > + dev_warn(&pdev->dev,
> > + "ignoring PCIe DT node, missing pcie-port property\n");
> > + continue;
> > + }
> > +
> > + if (of_property_read_u32(child, "marvell,pcie-lane",
> > + &port->lane))
> > + port->lane = 0;
> > +
> > + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
> > + port->port, port->lane);
> > +
> > + port->devfn = of_pci_get_devfn(child);
> > + if (port->devfn < 0)
> > + continue;
> > +
> > + port->base = mvebu_pcie_map_registers(pdev, child, port);
> > + if (!port->base) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
> > + port->port, port->lane);
> > + continue;
> > + }
> > +
> > + if (mvebu_pcie_link_up(port)) {
> > + port->haslink = 1;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
> > + port->port, port->lane);
> > + } else {
> > + port->haslink = 0;
> > + dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
> > + port->port, port->lane);
> > + }
> > +
> > + port->clk = of_clk_get_by_name(child, NULL);
> > + if (!port->clk) {
> > + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
> > + port->port, port->lane);
> > + iounmap(port->base);
> > + port->haslink = 0;
> > + continue;
> > + }
> > +
> > + port->dn = child;
> > +
> > + clk_prepare_enable(port->clk);
> > + spin_lock_init(&port->conf_lock);
> > +
> > + mvebu_sw_pci_bridge_init(port);
> > +
> > + i++;
> > + }
> > +
> > + mvebu_pcie_enable(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mvebu_pcie_of_match_table[] = {
> > + { .compatible = "marvell,armada-xp-pcie", },
> > + { .compatible = "marvell,armada-370-pcie", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
> > +
> > +static struct platform_driver mvebu_pcie_driver = {
> > + .driver = {
> > + .owner = THIS_MODULE,
> > + .name = "mvebu-pcie",
> > + .of_match_table =
> > + of_match_ptr(mvebu_pcie_of_match_table),
> > + },
> > +};
> > +
> > +static int mvebu_pcie_init(void)
>
> Building this showed a warning here. It seems you forgot
> to mark this one as __init.
Thomas, I'll fix this up when I pull this in, no need to resend. :)
thx,
Jason.
next prev parent reply other threads:[~2013-05-16 15:41 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-15 13:25 [PATCHv9 0/9] PCIe support for the Armada 370 and Armada XP SoCs Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 1/9] arm: mvebu: fix the 'ranges' property to handle PCIe Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 2/9] of/pci: Provide support for parsing PCI DT ranges property Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 3/9] of/pci: Add of_pci_get_devfn() function Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 4/9] of/pci: Add of_pci_parse_bus_range() function Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 21:41 ` Mike Turquette
2013-05-15 21:41 ` Mike Turquette
2013-05-16 7:44 ` Thomas Petazzoni
2013-05-16 7:44 ` Thomas Petazzoni
2013-05-16 8:26 ` Sebastian Hesselbarth
2013-05-16 8:26 ` Sebastian Hesselbarth
2013-05-16 15:06 ` Jason Cooper
2013-05-16 15:06 ` Jason Cooper
2013-05-16 15:06 ` Jason Cooper
2013-05-17 7:08 ` Mike Turquette
2013-05-17 7:08 ` Mike Turquette
2013-05-17 12:55 ` Jason Cooper
2013-05-17 12:55 ` Jason Cooper
2013-05-17 12:55 ` Jason Cooper
2013-05-15 13:25 ` [PATCHv9 6/9] clk: mvebu: add more PCIe clocks for Armada XP Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 7/9] pci: PCIe driver for Marvell Armada 370/XP systems Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-16 9:33 ` Ezequiel Garcia
2013-05-16 9:33 ` Ezequiel Garcia
2013-05-16 15:40 ` Jason Cooper [this message]
2013-05-16 15:40 ` Jason Cooper
2013-05-16 15:40 ` Jason Cooper
2013-05-16 15:49 ` Thomas Petazzoni
2013-05-16 15:49 ` Thomas Petazzoni
2013-05-16 15:56 ` Jason Cooper
2013-05-16 15:56 ` Jason Cooper
2013-05-16 15:56 ` Jason Cooper
2013-05-16 16:08 ` Thomas Petazzoni
2013-05-16 16:08 ` Thomas Petazzoni
2013-05-16 16:12 ` Jason Cooper
2013-05-16 16:12 ` Jason Cooper
2013-05-16 16:12 ` Jason Cooper
2013-05-16 20:18 ` Jason Cooper
2013-05-16 20:18 ` Jason Cooper
2013-05-16 20:18 ` Jason Cooper
2013-05-15 13:25 ` [PATCHv9 8/9] arm: mvebu: PCIe support is now available on mvebu Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
2013-05-15 13:25 ` [PATCHv9 9/9] arm: mvebu: update defconfig with PCI and USB support Thomas Petazzoni
2013-05-15 13:25 ` Thomas Petazzoni
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