From: Simon Horman <horms@verge.net.au>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/4] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Date: Wed, 05 Jun 2013 13:51:36 +0000 [thread overview]
Message-ID: <20130605135136.GC7451@verge.net.au> (raw)
In-Reply-To: <201306051352.52924.arnd@arndb.de>
On Wed, Jun 05, 2013 at 01:52:52PM +0200, Arnd Bergmann wrote:
> On Wednesday 05 June 2013, Simon Horman wrote:
> > @@ -0,0 +1,13 @@
> > +DT bindings for the R-/SH-Mobile irqpin controller
> > +
> > +Required properties:
> > +
> > +- compatible: has to be "renesas,intc-irqpin"
> > +- #interrupt-cells: has to be <2>
> > +
> > +Optional properties:
> > +
> > +- any properties, listed in interrupts.txt in this directory, and any standard
> > + resource allocation properties
> > +- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
> > + if different from the default 4 bits
>
> I think you should add documentation here about how the two interrupt cells
> are to be interpreted, to allow people to fill the values from a data sheet
> or board schematic.
I will drop this patch from the renesas tree pending some more work
on the documentation.
I'll put together an updated pull request for renesas-intc-irqpin
without this or the runtime-pm patch, which Magnus commented on elsewhere.
WARNING: multiple messages have this Message-ID (diff)
From: horms@verge.net.au (Simon Horman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Date: Wed, 5 Jun 2013 22:51:36 +0900 [thread overview]
Message-ID: <20130605135136.GC7451@verge.net.au> (raw)
In-Reply-To: <201306051352.52924.arnd@arndb.de>
On Wed, Jun 05, 2013 at 01:52:52PM +0200, Arnd Bergmann wrote:
> On Wednesday 05 June 2013, Simon Horman wrote:
> > @@ -0,0 +1,13 @@
> > +DT bindings for the R-/SH-Mobile irqpin controller
> > +
> > +Required properties:
> > +
> > +- compatible: has to be "renesas,intc-irqpin"
> > +- #interrupt-cells: has to be <2>
> > +
> > +Optional properties:
> > +
> > +- any properties, listed in interrupts.txt in this directory, and any standard
> > + resource allocation properties
> > +- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
> > + if different from the default 4 bits
>
> I think you should add documentation here about how the two interrupt cells
> are to be interpreted, to allow people to fill the values from a data sheet
> or board schematic.
I will drop this patch from the renesas tree pending some more work
on the documentation.
I'll put together an updated pull request for renesas-intc-irqpin
without this or the runtime-pm patch, which Magnus commented on elsewhere.
next prev parent reply other threads:[~2013-06-05 13:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-05 4:32 [PATCH 0/4] Update for Renesas INTC External IRQ pin driver for v3.11 Simon Horman
2013-06-05 4:32 ` Simon Horman
2013-06-05 4:32 ` [PATCH 1/4] irqchip: irqc: Add runtime PM support Simon Horman
2013-06-05 4:32 ` Simon Horman
2013-06-05 7:03 ` Magnus Damm
2013-06-05 7:03 ` Magnus Damm
2013-06-05 13:49 ` Simon Horman
2013-06-05 13:49 ` Simon Horman
2013-06-05 4:32 ` [PATCH 2/4] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Simon Horman
2013-06-05 4:32 ` Simon Horman
2013-06-05 11:52 ` Arnd Bergmann
2013-06-05 11:52 ` Arnd Bergmann
2013-06-05 13:51 ` Simon Horman [this message]
2013-06-05 13:51 ` Simon Horman
2013-06-05 4:32 ` [PATCH 3/4] irqchip: renesas-irqc: Fix irqc_probe error handling Simon Horman
2013-06-05 4:32 ` Simon Horman
2013-06-05 4:32 ` [PATCH 4/4] irqchip: Add irqchip_init dummy function Simon Horman
2013-06-05 4:32 ` Simon Horman
2013-06-05 6:45 ` [GIT PULL 0/4] Update for Renesas INTC External IRQ pin driver for v3.11 Simon Horman
2013-06-05 6:45 ` Simon Horman
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