Playing with the idea of pulling kernel code into i-g-t

Playing with the idea of pulling kernel code into i-g-t

[Damien Lespiau]

I played a bit with this as that's something thas has been floating around for
a bit and could be used for:
  - unit testing kernel functions (eg. PLL computations)
  - reuse off some code (intel_reg.h, sideband, device_info struct, ...)
  - Ville wanted to fuzzy test the EDID code (and has a branch somewhere IIRC)
  - ...

To make it maintainable we could have a script that, when pointed to a kernel,
pulls in the needed pieces. A simple form of this is scripts/sync-from-kernel
in the following patch.

$ ./scripts/sync-from-kernel ../linux-2.6/
Using v3.9-rc1-15371-g393f670
Importing intel_sideband.c

You then need a shim layer that replicates what we use from the kernel. A lot
can probably be faked without too much trouble.

A good use case for that would be to be able to have one master copy of
i915_reg.h (the kernel's) and sync it into i-g-t.

In any case, the following patch pulls in intel_sideband.c and replaces what we
currenlty have. It's aboslutely not tested and might just end up being a
pointless exercise...

-- 
Damien

[RFC] lib: Import intel_sideband.c from the kernel

[Damien Lespiau]

XXX: more detailed commit message
---
 lib/Makefile.am                                    |   9 +-
 lib/intel_dpio.c                                   |  94 ---------
 lib/intel_gpu_tools.h                              |  15 ++
 lib/intel_iosf.c                                   |  85 --------
 lib/intel_reg.h                                    | 221 +++++++++++++++++++--
 lib/intel_sideband.c                               | 191 ++++++++++++++++++
 tools/intel_dpio_read.c => lib/intel_sideband.h    |  64 ++----
 .../kernel-shim/drm-shim.h                         |  62 +++---
 .../kernel-shim/i915_drv.h                         |  53 ++---
 .../kernel-shim/intel_drv.h                        |  69 +++----
 .../intel_dpio_read.c => lib/kernel-shim/kernel.h  |  76 +++----
 scripts/sync-from-kernel                           |  30 +++
 tools/intel_dpio_read.c                            |   4 +-
 tools/intel_dpio_write.c                           |   4 +-
 tools/intel_nc_read.c                              |   6 +-
 tools/intel_nc_write.c                             |  10 +-
 tools/intel_punit_read.c                           |   6 +-
 tools/intel_punit_write.c                          |  10 +-
 18 files changed, 592 insertions(+), 417 deletions(-)
 delete mode 100644 lib/intel_dpio.c
 delete mode 100644 lib/intel_iosf.c
 create mode 100644 lib/intel_sideband.c
 copy tools/intel_dpio_read.c => lib/intel_sideband.h (52%)
 copy tools/intel_dpio_write.c => lib/kernel-shim/drm-shim.h (55%)
 copy tools/intel_dpio_write.c => lib/kernel-shim/i915_drv.h (55%)
 copy tools/intel_dpio_write.c => lib/kernel-shim/intel_drv.h (55%)
 copy tools/intel_dpio_read.c => lib/kernel-shim/kernel.h (52%)
 create mode 100755 scripts/sync-from-kernel

diff --git a/lib/Makefile.am b/lib/Makefile.am
index 387141b..2cafe22 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -1,10 +1,14 @@
 
 noinst_LTLIBRARIES = libintel_tools.la
 
-AM_CPPFLAGS = -I$(top_srcdir)
+AM_CPPFLAGS = -I$(top_srcdir) -I$(srcdir)/kernel-shim
 AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS)
 
 libintel_tools_la_SOURCES = 	\
+	kernel-shim/kernel.h	\
+	kernel-shim/i915_drv.h	\
+	kernel-shim/intel_drv.h	\
+	kernel-shim/drm-shim.h	\
 	debug.h			\
 	drmtest.c		\
 	drmtest.h		\
@@ -29,8 +33,7 @@ libintel_tools_la_SOURCES = 	\
 	rendercopy_gen7.c	\
 	rendercopy.h		\
 	intel_reg_map.c		\
-	intel_dpio.c		\
-	intel_iosf.c		\
+	intel_sideband.c	\
 	$(NULL)
 
 LDADD = $(CAIRO_LIBS)
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
deleted file mode 100644
index acfd201..0000000
--- a/lib/intel_dpio.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright © 2008 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Vijay Purushothaman <vijay.a.purushothaman@intel.com>
- *
- */
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include "intel_gpu_tools.h"
-
-static uint32_t intel_display_reg_read(uint32_t reg)
-{
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (IS_VALLEYVIEW(dev->device_id))
-		reg += VLV_DISPLAY_BASE;
-	return (*(volatile uint32_t*)((volatile char*)mmio + reg));
-}
-
-static void intel_display_reg_write(uint32_t reg, uint32_t val)
-{
-	volatile uint32_t *ptr;
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (IS_VALLEYVIEW(dev->device_id))
-		reg += VLV_DISPLAY_BASE;
-	ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
-	*ptr = val;
-}
-
-/*
- * In SoCs like Valleyview some of the PLL & Lane control registers
- * can be accessed only through IO side band fabric called DPIO
- */
-uint32_t
-intel_dpio_reg_read(uint32_t reg)
-{
-	/* Check whether the side band fabric is ready to accept commands */
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	intel_display_reg_write(DPIO_REG, reg);
-	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-						DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	return intel_display_reg_read(DPIO_DATA);
-}
-
-/*
- * In SoCs like Valleyview some of the PLL & Lane control registers
- * can be accessed only through IO side band fabric called DPIO
- */
-void
-intel_dpio_reg_write(uint32_t reg, uint32_t val)
-{
-	/* Check whether the side band fabric is ready to accept commands */
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	intel_display_reg_write(DPIO_DATA, val);
-	intel_display_reg_write(DPIO_REG, reg);
-	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-						DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-}
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index faa948c..bd54171 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -112,4 +112,19 @@ void intel_check_pch(void);
 #define HAS_CPT (pch == PCH_CPT)
 #define HAS_LPT (pch == PCH_LPT)
 
+/*
+ * Kernel Shim
+ */
+
+/* Don't really care about locking atm */
+struct mutex
+{
+	int dummy;
+};
+
+struct drm_i915_private
+{
+	struct mutex dpio_lock;
+};
+
 #endif /* INTEL_GPU_TOOLS_H */
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
deleted file mode 100644
index 0ab14df..0000000
--- a/lib/intel_iosf.c
+++ /dev/null
@@ -1,85 +0,0 @@
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include <errno.h>
-#include "intel_gpu_tools.h"
-
-#define TIMEOUT_US 500000
-
-static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
-			uint32_t *val)
-{
-	volatile uint32_t *ptr;
-	int timeout = 0;
-	uint32_t cmd, devfn, be, bar;
-
-	bar = 0;
-	be = 0xf;
-	devfn = 16;
-
-	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
-		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
-		(bar << IOSF_BAR_SHIFT);
-
-	ptr = (volatile uint32_t*)((volatile char*)mmio +
-				   VLV_IOSF_DOORBELL_REQ);
-
-	if (*ptr & IOSF_SB_BUSY) {
-		fprintf(stderr, "warning: pcode (%s) mailbox access failed\n",
-			opcode == PUNIT_OPCODE_REG_READ ?
-			"read" : "write");
-		return -EAGAIN;
-	}
-
-	ptr = (volatile uint32_t*)((volatile char*)mmio + VLV_IOSF_ADDR);
-	*ptr = addr;
-	if (opcode == PUNIT_OPCODE_REG_WRITE) {
-		ptr = (volatile uint32_t*)((volatile char*)mmio +
-					   VLV_IOSF_DATA);
-		*ptr = *val;
-	}
-	ptr = (volatile uint32_t*)((volatile char*)mmio +
-				   VLV_IOSF_DOORBELL_REQ);
-	*ptr = cmd;
-	do {
-		usleep(1);
-		timeout++;
-	} while ((*ptr & IOSF_SB_BUSY) && timeout < TIMEOUT_US);
-
-	if (timeout >= TIMEOUT_US) {
-		fprintf(stderr, "timeout waiting for pcode %s (%d) to finish\n",
-			opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
-			addr);
-		return -ETIMEDOUT;
-	}
-
-	if (opcode == PUNIT_OPCODE_REG_READ) {
-		ptr = (volatile uint32_t*)((volatile char*)mmio +
-					   VLV_IOSF_DATA);
-		*val = *ptr;
-	}
-	*ptr = 0;
-
-	return 0;
-}
-
-int intel_punit_read(uint8_t addr, uint32_t *val)
-{
-	return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
-}
-
-int intel_punit_write(uint8_t addr, uint32_t val)
-{
-	return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
-}
-
-int intel_nc_read(uint8_t addr, uint32_t *val)
-{
-	return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
-}
-
-int intel_nc_write(uint8_t addr, uint32_t val)
-{
-	return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
-}
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 065881b..173919c 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3549,20 +3549,12 @@ typedef enum {
 
 /* Valleyview related items */
 
-/* Valleyview DPIO registers */
 #define VLV_DISPLAY_BASE	0x180000
-#define DPIO_PKT			0x2100
-#define  DPIO_RID			(0 << 24)
-#define  DPIO_OP_WRITE		(1 << 16)
-#define  DPIO_OP_READ		(0 << 16)
-#define  DPIO_PORTID		(0x12 << 8)
-#define  DPIO_BYTE			(0xf << 4)
-#define  DPIO_BUSY			(1 << 0)
-#define DPIO_DATA			0x2104
-#define DPIO_REG			0x2108
-
-/* VLV IOSF access */
-#define VLV_IOSF_DOORBELL_REQ			0x182100
+
+/*
+ * IOSF sideband
+ */
+#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
 #define   IOSF_DEVFN_SHIFT			24
 #define   IOSF_OPCODE_SHIFT			16
 #define   IOSF_PORT_SHIFT			8
@@ -3571,10 +3563,209 @@ typedef enum {
 #define   IOSF_SB_BUSY				(1<<0)
 #define   IOSF_PORT_PUNIT			0x4
 #define   IOSF_PORT_NC				0x11
-#define VLV_IOSF_DATA				0x182104
-#define VLV_IOSF_ADDR				0x182108
+#define   IOSF_PORT_DPIO			0x12
+#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
+#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 
 #define PUNIT_OPCODE_REG_READ			6
 #define PUNIT_OPCODE_REG_WRITE			7
 
+#define PUNIT_REG_GPU_LFM			0xd3
+#define PUNIT_REG_GPU_FREQ_REQ			0xd4
+#define PUNIT_REG_GPU_FREQ_STS			0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
+
+#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
+
+#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
+#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
+#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
+#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
+#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
+#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
+#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
+#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
+#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
+#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
+
+/*
+ * DPIO - a special bus for various display related registers to hide behind
+ *
+ * DPIO is VLV only.
+ *
+ * Note: digital port B is DDI0, digital port C is DDI1
+ */
+#define DPIO_DEVFN			0
+#define DPIO_OPCODE_REG_WRITE		1
+#define DPIO_OPCODE_REG_READ		0
+
+#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
+#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
+#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
+#define  DPIO_SFR_BYPASS		(1<<1)
+#define  DPIO_RESET			(1<<0)
+
+#define _DPIO_TX3_SWING_CTL4_A		0x690
+#define _DPIO_TX3_SWING_CTL4_B		0x2a90
+#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
+					_DPIO_TX3_SWING_CTL4_B)
+
+/*
+ * Per pipe/PLL DPIO regs
+ */
+#define _DPIO_DIV_A			0x800c
+#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
+#define   DPIO_POST_DIV_DAC		0
+#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
+#define   DPIO_POST_DIV_LVDS1		2
+#define   DPIO_POST_DIV_LVDS2		3
+#define   DPIO_K_SHIFT			(24) /* 4 bits */
+#define   DPIO_P1_SHIFT			(21) /* 3 bits */
+#define   DPIO_P2_SHIFT			(16) /* 5 bits */
+#define   DPIO_N_SHIFT			(12) /* 4 bits */
+#define   DPIO_ENABLE_CALIBRATION	(1<<11)
+#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
+#define   DPIO_M2DIV_MASK		0xff
+#define _DPIO_DIV_B			0x802c
+#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
+
+#define _DPIO_REFSFR_A			0x8014
+#define   DPIO_REFSEL_OVERRIDE		27
+#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
+#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
+#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_PLL_REFCLK_SEL_MASK	3
+#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
+#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
+#define _DPIO_REFSFR_B			0x8034
+#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
+
+#define _DPIO_CORE_CLK_A		0x801c
+#define _DPIO_CORE_CLK_B		0x803c
+#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
+
+#define _DPIO_IREF_CTL_A		0x8040
+#define _DPIO_IREF_CTL_B		0x8060
+#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
+
+#define DPIO_IREF_BCAST			0xc044
+#define _DPIO_IREF_A			0x8044
+#define _DPIO_IREF_B			0x8064
+#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
+
+#define _DPIO_PLL_CML_A			0x804c
+#define _DPIO_PLL_CML_B			0x806c
+#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
+
+#define _DPIO_LFP_COEFF_A		0x8048
+#define _DPIO_LFP_COEFF_B		0x8068
+#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
+
+#define DPIO_CALIBRATION		0x80ac
+
+#define DPIO_FASTCLK_DISABLE		0x8100
+
+/*
+ * Per DDI channel DPIO regs
+ */
+
+#define _DPIO_PCS_TX_0			0x8200
+#define _DPIO_PCS_TX_1			0x8400
+#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
+#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
+#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
+
+#define _DPIO_PCS_CLK_0			0x8204
+#define _DPIO_PCS_CLK_1			0x8404
+#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
+#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
+#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
+#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
+#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
+
+#define _DPIO_PCS_CTL_OVR1_A		0x8224
+#define _DPIO_PCS_CTL_OVR1_B		0x8424
+#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
+				       _DPIO_PCS_CTL_OVR1_B)
+
+#define _DPIO_PCS_STAGGER0_A		0x822c
+#define _DPIO_PCS_STAGGER0_B		0x842c
+#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
+				      _DPIO_PCS_STAGGER0_B)
+
+#define _DPIO_PCS_STAGGER1_A		0x8230
+#define _DPIO_PCS_STAGGER1_B		0x8430
+#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
+				      _DPIO_PCS_STAGGER1_B)
+
+#define _DPIO_PCS_CLOCKBUF0_A		0x8238
+#define _DPIO_PCS_CLOCKBUF0_B		0x8438
+#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
+				       _DPIO_PCS_CLOCKBUF0_B)
+
+#define _DPIO_PCS_CLOCKBUF8_A		0x825c
+#define _DPIO_PCS_CLOCKBUF8_B		0x845c
+#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
+				       _DPIO_PCS_CLOCKBUF8_B)
+
+#define _DPIO_TX_SWING_CTL2_A		0x8288
+#define _DPIO_TX_SWING_CTL2_B		0x8488
+#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
+				       _DPIO_TX_SWING_CTL2_B)
+
+#define _DPIO_TX_SWING_CTL3_A		0x828c
+#define _DPIO_TX_SWING_CTL3_B		0x848c
+#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
+				       _DPIO_TX_SWING_CTL3_B)
+
+#define _DPIO_TX_SWING_CTL4_A		0x8290
+#define _DPIO_TX_SWING_CTL4_B		0x8490
+#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
+				       _DPIO_TX_SWING_CTL4_B)
+
+#define _DPIO_TX_OCALINIT_0		0x8294
+#define _DPIO_TX_OCALINIT_1		0x8494
+#define   DPIO_TX_OCALINIT_EN		(1<<31)
+#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
+				     _DPIO_TX_OCALINIT_1)
+
+#define _DPIO_TX_CTL_0			0x82ac
+#define _DPIO_TX_CTL_1			0x84ac
+#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
+
+#define _DPIO_TX_LANE_0			0x82b8
+#define _DPIO_TX_LANE_1			0x84b8
+#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
+
+#define _DPIO_DATA_CHANNEL1		0x8220
+#define _DPIO_DATA_CHANNEL2		0x8420
+#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
+
+#define _DPIO_PORT0_PCS0		0x0220
+#define _DPIO_PORT0_PCS1		0x0420
+#define _DPIO_PORT1_PCS2		0x2620
+#define _DPIO_PORT1_PCS3		0x2820
+#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
+#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
+#define DPIO_DATA_CHANNEL1              0x8220
+#define DPIO_DATA_CHANNEL2              0x8420
+
+/* Sideband Interface (SBI) is programmed indirectly, via
+ * SBI_ADDR, which contains the register offset; and SBI_DATA,
+ * which contains the payload */
+#define SBI_ADDR			0xC6000
+#define SBI_DATA			0xC6004
+#define SBI_CTL_STAT			0xC6008
+#define  SBI_CTL_DEST_ICLK		(0x0<<16)
+#define  SBI_CTL_DEST_MPHY		(0x1<<16)
+#define  SBI_CTL_OP_IORD		(0x2<<8)
+#define  SBI_CTL_OP_IOWR		(0x3<<8)
+#define  SBI_CTL_OP_CRRD		(0x6<<8)
+#define  SBI_CTL_OP_CRWR		(0x7<<8)
+#define  SBI_RESPONSE_FAIL		(0x1<<1)
+#define  SBI_RESPONSE_SUCCESS		(0x0<<1)
+#define  SBI_BUSY			(0x1<<0)
+#define  SBI_READY			(0x0<<0)
+
 #endif /* _I810_REG_H */
diff --git a/lib/intel_sideband.c b/lib/intel_sideband.c
new file mode 100644
index 0000000..0271944
--- /dev/null
+++ b/lib/intel_sideband.c
@@ -0,0 +1,191 @@
+/*
+ * This file is generated from scripts/sync-from-kernel, do not hand-edit.
+ * This file is is from kernel v3.9-rc1-15371-g393f670
+ */
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+/* IOSF sideband */
+static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
+			   u32 port, u32 opcode, u32 addr, u32 *val)
+{
+	u32 cmd, be = 0xf, bar = 0;
+	bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
+			opcode == DPIO_OPCODE_REG_READ);
+
+	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
+		(bar << IOSF_BAR_SHIFT);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
+		DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
+				 is_read ? "read" : "write");
+		return -EAGAIN;
+	}
+
+	I915_WRITE(VLV_IOSF_ADDR, addr);
+	if (!is_read)
+		I915_WRITE(VLV_IOSF_DATA, *val);
+	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
+		DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
+				 is_read ? "read" : "write");
+		return -ETIMEDOUT;
+	}
+
+	if (is_read)
+		*val = I915_READ(VLV_IOSF_DATA);
+	I915_WRITE(VLV_IOSF_DATA, 0);
+
+	return 0;
+}
+
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
+			PUNIT_OPCODE_REG_READ, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+
+void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
+			PUNIT_OPCODE_REG_WRITE, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
+u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
+			PUNIT_OPCODE_REG_READ, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+
+void vlv_nc_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
+			PUNIT_OPCODE_REG_WRITE, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
+{
+	u32 val = 0;
+
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
+			DPIO_OPCODE_REG_READ, reg, &val);
+
+	return val;
+}
+
+void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
+{
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
+			DPIO_OPCODE_REG_WRITE, reg, &val);
+}
+
+/* SBI access */
+u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
+		   enum intel_sbi_destination destination)
+{
+	u32 value = 0;
+	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
+				100)) {
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+		return 0;
+	}
+
+	I915_WRITE(SBI_ADDR, (reg << 16));
+
+	if (destination == SBI_ICLK)
+		value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
+	else
+		value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
+	I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
+				100)) {
+		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
+		return 0;
+	}
+
+	return I915_READ(SBI_DATA);
+}
+
+void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
+		     enum intel_sbi_destination destination)
+{
+	u32 tmp;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
+				100)) {
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+		return;
+	}
+
+	I915_WRITE(SBI_ADDR, (reg << 16));
+	I915_WRITE(SBI_DATA, value);
+
+	if (destination == SBI_ICLK)
+		tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
+	else
+		tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
+	I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
+				100)) {
+		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
+		return;
+	}
+}
diff --git a/tools/intel_dpio_read.c b/lib/intel_sideband.h
similarity index 52%
copy from tools/intel_dpio_read.c
copy to lib/intel_sideband.h
index c0c904a..45892f5 100644
--- a/tools/intel_dpio_read.c
+++ b/lib/intel_sideband.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -17,52 +17,30 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *		Vijay Purushothaman <vijay.a.purushothaman@intel.com>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  *
  */
 
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include <string.h>
-#include "intel_gpu_tools.h"
-
-static void usage(char *cmdname)
-{
-	printf("Warning : This program will work only on Valleyview\n");
-	printf("Usage: %s [addr]\n", cmdname);
-	printf("\t addr : in 0xXXXX format\n");
-}
-
-int main(int argc, char** argv)
-{
-	int ret = 0;
-	uint32_t reg, val;
-	char *cmdname = strdup(argv[0]);
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
-		usage(cmdname);
-		ret = 1;
-		goto out;
-	}
-
-	sscanf(argv[1], "0x%x", &reg);
-
-	intel_register_access_init(dev, 0);
+#ifndef _INTEL_SIDEBAND_H_
+#define _INTEL_SIDEBAND_H_
 
-	val = intel_dpio_reg_read(reg);
+#include <stdint.h>
 
-	printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
+enum intel_sbi_destination {
+	SBI_ICLK,
+	SBI_MPHY,
+};
 
-	intel_register_access_fini();
+uint32_t vlv_punit_read(struct drm_i915_private *dev_priv, uint8_t addr);
+void vlv_punit_write(struct drm_i915_private *dev_priv, uint8_t addr, uint32_t val);
+uint32_t vlv_nc_read(struct drm_i915_private *dev_priv, uint8_t addr);
+void vlv_nc_write(struct drm_i915_private *dev_priv, uint8_t addr, uint32_t val);
+uint32_t vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, uint32_t val);
+uint32_t intel_sbi_read(struct drm_i915_private *dev_priv, uint16_t reg,
+                   enum intel_sbi_destination destination);
+void intel_sbi_write(struct drm_i915_private *dev_priv, uint16_t reg, uint32_t value,
+                     enum intel_sbi_destination destination);
 
-out:
-	free(cmdname);
-	return ret;
-}
+#endif /* _INTEL_SIDEBAND_H_ */
diff --git a/tools/intel_dpio_write.c b/lib/kernel-shim/drm-shim.h
similarity index 55%
copy from tools/intel_dpio_write.c
copy to lib/kernel-shim/drm-shim.h
index f842999..a88cf16 100644
--- a/tools/intel_dpio_write.c
+++ b/lib/kernel-shim/drm-shim.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -17,51 +17,39 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *		Vijay Purushothaman <vijay.a.purushothaman@intel.com>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  *
  */
 
-#include <unistd.h>
-#include <stdlib.h>
+#ifndef _DRM_SHIM_H_
+#define _DRM_SHIM_H_
+
 #include <stdio.h>
-#include <err.h>
-#include <string.h>
-#include "intel_gpu_tools.h"
 
-static void usage(char *cmdname)
-{
-	printf("Warning : This program will work only on Valleyview\n");
-	printf("Usage: %s [addr] [val]\n", cmdname);
-	printf("\t addr : in 0xXXXX format\n");
-}
+#define xstringify(s) #s
+#define stringify(s) xstringify(s)
 
-int main(int argc, char** argv)
-{
-	int ret = 0;
-	uint32_t reg, val;
-	char *cmdname = strdup(argv[0]);
-	struct pci_device *dev = intel_get_pci_device();
+#define STRLOC __FILE__ ":" stringify(__LINE__)
 
-	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
-		usage(cmdname);
-		ret = 1;
-		goto out;
-	}
+#define DRM_ERROR(fmt, args...) ({			\
+	fprintf(stderr, "%s" fmt, STRLOC ": ", ##args);	\
+})
 
-	sscanf(argv[1], "0x%x", &reg);
-	sscanf(argv[2], "0x%x", &val);
+#define DRM_INFO(fmt, args...) ({			\
+	fprintf(stdout, "%s" fmt, STRLOC ": ", ##args);	\
+})
 
-	intel_register_access_init(dev, 0);
+#define DRM_DEBUG(fmt, args...) ({			\
+	fprintf(stderr, "%s" fmt, STRLOC ": ", ##args);	\
+})
 
-	intel_dpio_reg_write(reg, val);
+#define DRM_DEBUG_DRIVER(fmt, args...) ({		\
+	fprintf(stderr, "%s" fmt, STRLOC ": ", ##args);	\
+})
 
-	intel_register_access_fini();
+#define DRM_DEBUG_KMS(fmt, args...) ({			\
+	fprintf(stderr, "%s" fmt, STRLOC ": ", ##args);	\
+})
 
-out:
-	free(cmdname);
-	return ret;
-}
+#endif /* _DRM_SHIM_H_ */
diff --git a/tools/intel_dpio_write.c b/lib/kernel-shim/i915_drv.h
similarity index 55%
copy from tools/intel_dpio_write.c
copy to lib/kernel-shim/i915_drv.h
index f842999..16d9d90 100644
--- a/tools/intel_dpio_write.c
+++ b/lib/kernel-shim/i915_drv.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -17,51 +17,22 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *		Vijay Purushothaman <vijay.a.purushothaman@intel.com>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  *
  */
 
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include <string.h>
-#include "intel_gpu_tools.h"
-
-static void usage(char *cmdname)
-{
-	printf("Warning : This program will work only on Valleyview\n");
-	printf("Usage: %s [addr] [val]\n", cmdname);
-	printf("\t addr : in 0xXXXX format\n");
-}
+#ifndef _I915_DRV_H_
+#define _I915_DRV_H_
 
-int main(int argc, char** argv)
-{
-	int ret = 0;
-	uint32_t reg, val;
-	char *cmdname = strdup(argv[0]);
-	struct pci_device *dev = intel_get_pci_device();
+#include "kernel.h"
+#include "drm-shim.h"
 
-	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
-		usage(cmdname);
-		ret = 1;
-		goto out;
-	}
-
-	sscanf(argv[1], "0x%x", &reg);
-	sscanf(argv[2], "0x%x", &val);
-
-	intel_register_access_init(dev, 0);
+#include "intel_gpu_tools.h"
 
-	intel_dpio_reg_write(reg, val);
+#define I915_READ(reg)		intel_register_read((reg))
+#define I915_WRITE(reg, val)	intel_register_write((reg), (val))
 
-	intel_register_access_fini();
+#include "intel_sideband.h"
 
-out:
-	free(cmdname);
-	return ret;
-}
+#endif /* _I915_DRV_H_ */
diff --git a/tools/intel_dpio_write.c b/lib/kernel-shim/intel_drv.h
similarity index 55%
copy from tools/intel_dpio_write.c
copy to lib/kernel-shim/intel_drv.h
index f842999..582643b 100644
--- a/tools/intel_dpio_write.c
+++ b/lib/kernel-shim/intel_drv.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -17,51 +17,32 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *		Vijay Purushothaman <vijay.a.purushothaman@intel.com>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  *
  */
 
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include <string.h>
-#include "intel_gpu_tools.h"
-
-static void usage(char *cmdname)
-{
-	printf("Warning : This program will work only on Valleyview\n");
-	printf("Usage: %s [addr] [val]\n", cmdname);
-	printf("\t addr : in 0xXXXX format\n");
-}
-
-int main(int argc, char** argv)
-{
-	int ret = 0;
-	uint32_t reg, val;
-	char *cmdname = strdup(argv[0]);
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
-		usage(cmdname);
-		ret = 1;
-		goto out;
-	}
+#ifndef _INTEL_DRV_H_
+#define _INTEL_DRV_H_
 
-	sscanf(argv[1], "0x%x", &reg);
-	sscanf(argv[2], "0x%x", &val);
-
-	intel_register_access_init(dev, 0);
-
-	intel_dpio_reg_write(reg, val);
-
-	intel_register_access_fini();
+#include <unistd.h>
 
-out:
-	free(cmdname);
-	return ret;
-}
+#include "kernel.h"
+
+/* rather crude, but hopefully good enough */
+#define wait_for(COND, MS) ({				\
+	unsigned int elapsed_ms = 0;			\
+	int ret__  = 0;					\
+	while (!(COND)) {				\
+		if (elapsed_ms > (MS)) {		\
+			ret__ = -ETIMEDOUT;		\
+			break;				\
+		}					\
+							\
+		usleep(1000);				\
+		elapsed_ms++;				\
+	}						\
+	ret__;						\
+})
+
+#endif /* _INTEL_DRV_H_ */
diff --git a/tools/intel_dpio_read.c b/lib/kernel-shim/kernel.h
similarity index 52%
copy from tools/intel_dpio_read.c
copy to lib/kernel-shim/kernel.h
index c0c904a..e621408 100644
--- a/tools/intel_dpio_read.c
+++ b/lib/kernel-shim/kernel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2012 Intel Corporation
+ * Copyright © 2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -17,52 +17,54 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *		Vijay Purushothaman <vijay.a.purushothaman@intel.com>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  *
  */
 
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include <string.h>
+#ifndef _KERNEL_H_
+#define _KERNEL_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+
 #include "intel_gpu_tools.h"
 
-static void usage(char *cmdname)
+typedef uint64_t           u64;
+typedef int64_t            s64;
+typedef unsigned int       u32;
+typedef signed int         s32;
+typedef unsigned short     u16;
+typedef signed short       s16;
+typedef unsigned char      u8;
+typedef signed char        s8;
+
+static inline int mutex_is_locked(struct mutex *lock)
 {
-	printf("Warning : This program will work only on Valleyview\n");
-	printf("Usage: %s [addr]\n", cmdname);
-	printf("\t addr : in 0xXXXX format\n");
+	return 1;
 }
 
-int main(int argc, char** argv)
+static inline void mutex_lock(struct mutex *lock)
 {
-	int ret = 0;
-	uint32_t reg, val;
-	char *cmdname = strdup(argv[0]);
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
-		usage(cmdname);
-		ret = 1;
-		goto out;
-	}
-
-	sscanf(argv[1], "0x%x", &reg);
-
-	intel_register_access_init(dev, 0);
+}
 
-	val = intel_dpio_reg_read(reg);
+static inline void mutex_unlock(struct mutex *lock)
+{
+}
 
-	printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
+#define WARN_ON(cond)
 
-	intel_register_access_fini();
+/*
+ * The PCI interface treats multi-function devices as independent
+ * devices.  The slot/function address of each device is encoded
+ * in a single byte as follows:
+ *
+ *      7:3 = slot
+ *      2:0 = function
+ */
+#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
+#define PCI_FUNC(devfn)         ((devfn) & 0x07)
 
-out:
-	free(cmdname);
-	return ret;
-}
+#endif /* _KERNEL_TYPES_H_ */
diff --git a/scripts/sync-from-kernel b/scripts/sync-from-kernel
new file mode 100755
index 0000000..6940815
--- /dev/null
+++ b/scripts/sync-from-kernel
@@ -0,0 +1,30 @@
+#!/bin/bash
+
+kernel_path=$1
+[ -z "$kernel_path" ] && kernel_path=.
+
+[ -f $kernel_path/Kconfig ] || {
+	echo "$kernel_path is not a path to a kernel"
+	exit 1
+}
+
+kernel_description=$(cd $kernel_path; git describe)
+echo Using $kernel_description
+
+read -r -d '' header <<EOF
+/*
+ * This file is generated from scripts/sync-from-kernel, do not hand-edit.
+ * This file is is from kernel $kernel_description
+ */
+EOF
+
+function import {
+	src=$1
+	dst=$2
+
+	echo "Importing `basename $src`"
+	echo "$header" > $dst
+	cat $kernel_path/$src >> $dst
+}
+
+import "$kernel_path/drivers/gpu/drm/i915/intel_sideband.c" lib/intel_sideband.c
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
index c0c904a..52c6080 100644
--- a/tools/intel_dpio_read.c
+++ b/tools/intel_dpio_read.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -56,7 +58,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	val = intel_dpio_reg_read(reg);
+	val = vlv_dpio_read(&dev_priv, reg);
 
 	printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
 
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
index f842999..0d519c8 100644
--- a/tools/intel_dpio_write.c
+++ b/tools/intel_dpio_write.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -57,7 +59,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	intel_dpio_reg_write(reg, val);
+	vlv_dpio_write(&dev_priv, reg, val);
 
 	intel_register_access_fini();
 
diff --git a/tools/intel_nc_read.c b/tools/intel_nc_read.c
index a2c2e9f..3386305 100644
--- a/tools/intel_nc_read.c
+++ b/tools/intel_nc_read.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -56,9 +58,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	ret = intel_nc_read(reg, &val);
-	if (ret)
-		fprintf(stderr, "iosf read failed: %d\n", ret);
+	val = vlv_nc_read(&dev_priv, reg);
 
 	printf("Read IOSF register: 0x%x - Value : 0x%x\n", reg, val);
 
diff --git a/tools/intel_nc_write.c b/tools/intel_nc_write.c
index 58be79a..047269a 100644
--- a/tools/intel_nc_write.c
+++ b/tools/intel_nc_write.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val, tmp;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -57,14 +59,12 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	intel_nc_read(reg, &tmp);
+	tmp = vlv_nc_read(&dev_priv, reg);
 	printf("Value before: 0x%X\n", tmp);
 
-	ret = intel_nc_write(reg, val);
-	if (ret)
-		fprintf(stderr, "Nc write failed: %d\n", ret);
+	vlv_nc_write(&dev_priv, reg, val);
 
-	intel_nc_read(reg, &tmp);
+	tmp = vlv_nc_read(&dev_priv, reg);
 	printf("Value after: 0x%X\n", tmp);
 
 	intel_register_access_fini();
diff --git a/tools/intel_punit_read.c b/tools/intel_punit_read.c
index 3fa2ca8..4661825 100644
--- a/tools/intel_punit_read.c
+++ b/tools/intel_punit_read.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -56,9 +58,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	ret = intel_punit_read(reg, &val);
-	if (ret)
-		fprintf(stderr, "iosf read failed: %d\n", ret);
+	val = vlv_punit_read(&dev_priv, reg);
 
 	printf("Read IOSF register: 0x%x - Value : 0x%x\n", reg, val);
 
diff --git a/tools/intel_punit_write.c b/tools/intel_punit_write.c
index eb036ba..30d4522 100644
--- a/tools/intel_punit_write.c
+++ b/tools/intel_punit_write.c
@@ -31,6 +31,7 @@
 #include <err.h>
 #include <string.h>
 #include "intel_gpu_tools.h"
+#include "intel_sideband.h"
 
 static void usage(char *cmdname)
 {
@@ -45,6 +46,7 @@ int main(int argc, char** argv)
 	uint32_t reg, val, tmp;
 	char *cmdname = strdup(argv[0]);
 	struct pci_device *dev = intel_get_pci_device();
+	struct drm_i915_private dev_priv;
 
 	if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
 		usage(cmdname);
@@ -57,14 +59,12 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	intel_punit_read(reg, &tmp);
+	tmp = vlv_punit_read(&dev_priv, reg);
 	printf("Value before: 0x%X\n", tmp);
 
-	ret = intel_punit_write(reg, val);
-	if (ret)
-		fprintf(stderr, "Punit write failed: %d\n", ret);
+	vlv_punit_write(&dev_priv, reg, val);
 
-	intel_punit_read(reg, &tmp);
+	tmp = vlv_punit_read(&dev_priv, reg);
 	printf("Value after: 0x%X\n", tmp);
 
 	intel_register_access_fini();
-- 
1.8.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: Playing with the idea of pulling kernel code into i-g-t

[Ville Syrjälä]

On Wed, Jun 05, 2013 at 11:59:37AM +0100, Damien Lespiau wrote:
> 
> I played a bit with this as that's something thas has been floating around for
> a bit and could be used for:
>   - unit testing kernel functions (eg. PLL computations)
>   - reuse off some code (intel_reg.h, sideband, device_info struct, ...)
>   - Ville wanted to fuzzy test the EDID code (and has a branch somewhere IIRC)

So far I always forgot to push it anywhere. Now it's here:
git://gitorious.org/vsyrjala/drm_edid_test.git

It's just a copy drm_edid.c and some other files, a bunch of stubs make
it compile, and a small program that reads in an edid and prints a bunch
of stuff drm_edid.c managed to parse from it.

-- 
Ville Syrjälä
Intel OTC