[PATCH v4 2/6] clocksource: add Marvell Orion SoC timer

[andrew@lunn.ch (Andrew Lunn)]

On Mon, Jun 10, 2013 at 11:35:55AM +0200, Sebastian Hesselbarth wrote:
> This patch add a DT enabled driver for timers found on Marvell Orion SoCs
> (Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
> running clocksource on timer0 and a clockevent source on timer1.
> Corresponding device tree documentation is also added.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> v3->v4:
> - export thread-safe access to TIMER_CTRL register to use with watchdog
> - remove IRQF_DISABLED and add .irq to clock event (Suggested by Daniel Lezcano)
> 
> Notes:
> - This is only an update to clocksource driver, the remaining patches are
>   not resent as they have not been changed.
> - I will not rework orion watchdog driver for this patch set. It is written
>   Kirkwood/Orion5x specific although it will also work on Dove and it is messing
>   with shared registers. It has done it before, so I consider it broken anyway.
>   I (or somebody else) will take care of proper watchdog later.
> - An updated branch can be found on
>   git://github.com/shesselba/linux-dove.git orion-irqchip-for-v3.11_v4

Hi Sebastian

You can add a

Tested-by: Andrew Lunn <andrew@lunn.ch>

I tested on my kirkwood QNAP.

           CPU0
  2:       6062  bridge-interrupt-ctrl  orion_event
  9:          0  f1010140.gpio  Reset
 15:          0  f1010140.gpio  USB Copy
 24:        106  main-interrupt-ctrl  ehci_hcd:usb1
 25:       2463  main-interrupt-ctrl  sata_mv
 26:          0  main-interrupt-ctrl  f1030000.crypto
 27:          2  main-interrupt-ctrl  f1060800.xor
 28:          2  main-interrupt-ctrl  f1060800.xor
 29:         71  main-interrupt-ctrl  mv64xxx_i2c
 30:          2  main-interrupt-ctrl  f1060900.xor
 31:          2  main-interrupt-ctrl  f1060900.xor
 32:         41  main-interrupt-ctrl  eth0
 33:       1317  main-interrupt-ctrl  serial
 75:        745  main-interrupt-ctrl  f1072004.mdio-bus
Err:          0                                              

      Andrew