From: Thierry Reding <thierry.reding@gmail.com>
To: Jay Agarwal <jagarwal@nvidia.com>
Cc: linux@arm.linux.org.uk, swarren@wwwdotorg.org,
thierry.reding@avionic-design.de, bhelgaas@google.com,
ldewangan@nvidia.com, olof@lixom.net, hdoyu@nvidia.com,
pgaikwad@nvidia.com, mturquette@linaro.org,
pdeschrijver@nvidia.com, linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, jtukkinen@nvidia.com,
kthota@nvidia.com
Subject: Re: [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry
Date: Mon, 10 Jun 2013 21:55:12 +0200 [thread overview]
Message-ID: <20130610195511.GC25859@mithrandir> (raw)
In-Reply-To: <1370372252-4332-3-git-send-email-jagarwal@nvidia.com>
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On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
[...]
> @@ -29,7 +29,7 @@
> ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
> 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
> 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
> - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
> + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */
> 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */
> 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
That increases the I/O region size from 64 KiB to 1 MiB. Why is that
necessary? I/O operations can only address 64 KiB, so I don't think
adding more makes any sense.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry
Date: Mon, 10 Jun 2013 21:55:12 +0200 [thread overview]
Message-ID: <20130610195511.GC25859@mithrandir> (raw)
In-Reply-To: <1370372252-4332-3-git-send-email-jagarwal@nvidia.com>
On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
[...]
> @@ -29,7 +29,7 @@
> ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
> 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
> 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
> - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
> + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */
> 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */
> 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
That increases the I/O region size from 64 KiB to 1 MiB. Why is that
necessary? I/O operations can only address 64 KiB, so I don't think
adding more makes any sense.
Thierry
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next prev parent reply other threads:[~2013-06-10 19:55 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-04 18:57 [PATCH V3 1/4] ARM: tegra30: clocks: Fix pciex clock registration Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 18:57 ` [PATCH V3 2/4] ARM: tegra: pcie: Add tegra3 support Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 19:17 ` Stephen Warren
2013-06-04 19:17 ` Stephen Warren
2013-06-05 14:57 ` Jay Agarwal
2013-06-05 14:57 ` Jay Agarwal
2013-06-10 19:50 ` Thierry Reding
2013-06-10 19:50 ` Thierry Reding
2013-06-11 4:43 ` Jay Agarwal
2013-06-11 4:43 ` Jay Agarwal
2013-06-11 10:16 ` Thierry Reding
2013-06-11 10:16 ` Thierry Reding
2013-06-11 10:16 ` Thierry Reding
2013-06-11 10:40 ` Jay Agarwal
2013-06-11 10:40 ` Jay Agarwal
2013-06-04 18:57 ` [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-10 19:55 ` Thierry Reding [this message]
2013-06-10 19:55 ` Thierry Reding
2013-06-11 4:52 ` Jay Agarwal
2013-06-11 4:52 ` Jay Agarwal
2013-06-11 4:52 ` Jay Agarwal
2013-06-11 7:30 ` Peter De Schrijver
2013-06-11 7:30 ` Peter De Schrijver
2013-06-11 7:30 ` Peter De Schrijver
2013-07-17 4:56 ` Thierry Reding
2013-07-17 4:56 ` Thierry Reding
2013-07-17 4:56 ` Thierry Reding
2013-06-04 18:57 ` [PATCH V3 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 18:57 ` Jay Agarwal
2013-06-04 19:08 ` [PATCH V3 1/4] ARM: tegra30: clocks: Fix pciex clock registration Stephen Warren
2013-06-04 19:08 ` Stephen Warren
2013-06-11 22:17 ` Mike Turquette
2013-06-11 22:17 ` Mike Turquette
2013-06-12 7:11 ` Jay Agarwal
2013-06-12 7:11 ` Jay Agarwal
2013-06-12 7:11 ` Jay Agarwal
2013-06-12 7:11 ` Jay Agarwal
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