[PATCH 1/2] ARM: OMAP2+: gpmc: get number of useable GPMC chip-selects via DT

[PATCH 1/2] ARM: OMAP2+: gpmc: get number of useable GPMC chip-selects via DT

[Gupta, Pekon]

From: "Gupta, Pekon" <pekon@ti.com>

This patch enables usage of DT property 'gpmc,num-cs' as already documented in
Documentation/devicetree/bindings/bus/ti-gpmc.txt

Though GPMC hardware supports upto 8 chip-selects, but all chip-selects may
not be available for use because:
- chip-select pin may not be bonded out at SoC device boundary.
- chip-select pin-mux may conflict with other pins usage.
- board level constrains.

gpmc,num-cs allows user to configure maximum number of GPMC chip-selects
available for use on any given platform. This ensures:
- GPMC child nodes having chip-selects within allowed range are only probed.
- And un-used GPMC chip-selects remain blocked.(may be for security reasons).

Signed-off-by: Gupta, Pekon <pekon@ti.com>
---
 arch/arm/mach-omap2/gpmc.c | 38 +++++++++++++++++++++++++++++---------
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da12..490bca8 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -155,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
@@ -521,8 +522,10 @@ static int gpmc_cs_remap(int cs, u32 base)
 	int ret;
 	u32 old_base, size;
 
-	if (cs > GPMC_CS_NUM)
+	if (cs > gpmc_cs_num) {
+		pr_err("%s: requested chip-select is disabled\n", __func__);
 		return -ENODEV;
+	}
 	gpmc_cs_get_memconf(cs, &old_base, &size);
 	if (base == old_base)
 		return 0;
@@ -545,9 +548,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	struct resource *res = &gpmc_cs_mem[cs];
 	int r = -1;
 
-	if (cs > GPMC_CS_NUM)
+	if (cs > gpmc_cs_num) {
+		pr_err("%s: requested chip-select is disabled\n", __func__);
 		return -ENODEV;
-
+	}
 	size = gpmc_mem_align(size);
 	if (size > (1 << GPMC_SECTION_SHIFT))
 		return -ENOMEM;
@@ -582,7 +586,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
 void gpmc_cs_free(int cs)
 {
 	spin_lock(&gpmc_mem_lock);
-	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
+	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 		BUG();
 		spin_unlock(&gpmc_mem_lock);
@@ -777,7 +781,7 @@ static void gpmc_mem_exit(void)
 {
 	int cs;
 
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+	for (cs = 0; cs < gpmc_cs_num; cs++) {
 		if (!gpmc_cs_mem_enabled(cs))
 			continue;
 		gpmc_cs_delete_mem(cs);
@@ -798,7 +802,7 @@ static void gpmc_mem_init(void)
 	gpmc_mem_root.end = GPMC_MEM_END;
 
 	/* Reserve all regions that has been set up by bootloader */
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+	for (cs = 0; cs < gpmc_cs_num; cs++) {
 		u32 base, size;
 
 		if (!gpmc_cs_mem_enabled(cs))
@@ -1513,6 +1517,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
 	if (!of_id)
 		return 0;
 
+	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
+				   &gpmc_cs_num);
+	if (ret < 0) {
+		pr_err("%s: number of chip-selects not defined\n", __func__);
+		return ret;
+	} else if (gpmc_cs_num < 1) {
+		pr_err("%s: all chip-selects are disabled\n", __func__);
+		return -EINVAL;
+	} else if (gpmc_cs_num > GPMC_CS_NUM) {
+		pr_err("%s: number of supported chip-selects cannot be > %d\n",
+					 __func__, GPMC_CS_NUM);
+		return -EINVAL;
+	}
+
 	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
 				   &gpmc_nr_waitpins);
 	if (ret < 0) {
@@ -1610,8 +1628,10 @@ static int gpmc_probe(struct platform_device *pdev)
 	/* Now the GPMC is initialised, unreserve the chip-selects */
 	gpmc_cs_map = 0;
 
-	if (!pdev->dev.of_node)
+	if (!pdev->dev.of_node) {
+		gpmc_cs_num	 = GPMC_CS_NUM;
 		gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+	}
 
 	rc = gpmc_probe_dt(pdev);
 	if (rc < 0) {
@@ -1715,7 +1735,7 @@ void omap3_gpmc_save_context(void)
 	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
 	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
 	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
-	for (i = 0; i < GPMC_CS_NUM; i++) {
+	for (i = 0; i < gpmc_cs_num; i++) {
 		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
 		if (gpmc_context.cs_context[i].is_valid) {
 			gpmc_context.cs_context[i].config1 =
@@ -1747,7 +1767,7 @@ void omap3_gpmc_restore_context(void)
 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
 	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
-	for (i = 0; i < GPMC_CS_NUM; i++) {
+	for (i = 0; i < gpmc_cs_num; i++) {
 		if (gpmc_context.cs_context[i].is_valid) {
 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
 				gpmc_context.cs_context[i].config1);
-- 
1.8.1

[PATCH 2/2] ARM: OMAP2+: gpmc: removed 'gpmc,device-nand'. type determined from node-name

[Gupta, Pekon]

From: "Gupta, Pekon" <pekon@ti.com>

GPMC supports multiple types of child devices like NAND, NOR, OneNand, Ethernet
This patch removes 'gpmc,device-nand', used explicitely to specify NAND type
gpmc-child. Instead gpmc-child type can be inferred from gpmc->child->name.

Signed-off-by: Gupta, Pekon <pekon@ti.com>
---
 Documentation/devicetree/bindings/bus/ti-gpmc.txt | 1 -
 arch/arm/boot/dts/am335x-evm.dts                  | 1 -
 arch/arm/mach-omap2/gpmc-nand.c                   | 3 +--
 arch/arm/mach-omap2/gpmc-onenand.c                | 2 ++
 arch/arm/mach-omap2/gpmc.c                        | 1 -
 5 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 4b87ea1..704be93 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -95,7 +95,6 @@ GPMC chip-select settings properties for child nodes. All are optional.
 - gpmc,burst-wrap	Enables wrap bursting
 - gpmc,burst-read	Enables read page/burst mode
 - gpmc,burst-write	Enables write page/burst mode
-- gpmc,device-nand	Device is NAND
 - gpmc,device-width	Total width of device(s) connected to a GPMC
 			chip-select in bytes. The GPMC supports 8-bit
 			and 16-bit devices and so this property must be
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7d2be9c..c71bb77 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -136,7 +136,6 @@
 				reg = <0 0 0>; /* CS0, offset 0 */
 				nand-bus-width = <8>;
 				ti,nand-ecc-opt = "bch8";
-				gpmc,device-nand = "true";
 				gpmc,device-width = <1>;
 				gpmc,sync-clk-ps = <0>;
 				gpmc,cs-on-ns = <0>;
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c2719..dc50391 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -140,14 +140,13 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 		if (gpmc_nand_data->of_node) {
 			gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
 		} else {
-			s.device_nand = true;
-
 			/* Enable RD PIN Monitoring Reg */
 			if (gpmc_nand_data->dev_ready) {
 				s.wait_on_read = true;
 				s.wait_on_write = true;
 			}
 		}
+		s.device_nand = true;
 
 		if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
 			s.device_width = GPMC_DEVWIDTH_16BIT;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 64b5a83..cea4b6d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -275,6 +275,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
 	if (gpmc_onenand_data->of_node)
 		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
 				      &onenand_async);
+	onenand_async.device_nand = false;
 
 	omap2_onenand_set_async_mode(onenand_base);
 
@@ -315,6 +316,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
 		if (!cpu_is_omap34xx())
 			onenand_sync.wait_on_read = true;
 	}
+	onenand_sync.device_nand = false;
 
 	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 490bca8..fb6f241 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1249,7 +1249,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
 
 	p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
 	p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
-	p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
 	of_property_read_u32(np, "gpmc,device-width", &p->device_width);
 	of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
 
-- 
1.8.1

Re: [PATCH 2/2] ARM: OMAP2+: gpmc: removed 'gpmc,device-nand'. type determined from node-name

[Tony Lindgren]

* Gupta, Pekon <pekon@ti.com> [130531 05:07]:
> From: "Gupta, Pekon" <pekon@ti.com>
> 
> GPMC supports multiple types of child devices like NAND, NOR, OneNand, Ethernet
> This patch removes 'gpmc,device-nand', used explicitely to specify NAND type
> gpmc-child. Instead gpmc-child type can be inferred from gpmc->child->name.

This does not seem to apply. Also please break into a gpmc.c patch and
then the .dts patch for Benoit. And make sure you consider if removing
this binding might break something. If it does, we need to maintain the
support for the old binding.

Regards,

Tony

RE: [PATCH 2/2] ARM: OMAP2+: gpmc: removed 'gpmc,device-nand'. type determined from node-name

[Gupta, Pekon]

> > From: "Gupta, Pekon" <pekon@ti.com>
> >
> > GPMC supports multiple types of child devices like NAND, NOR, OneNand,
> Ethernet
> > This patch removes 'gpmc,device-nand', used explicitely to specify NAND
> type
> > gpmc-child. Instead gpmc-child type can be inferred from gpmc->child-
> >name.
> 
> This does not seem to apply. Also please break into a gpmc.c patch and
> then the .dts patch for Benoit. And make sure you consider if removing
> this binding might break something. If it does, we need to maintain the
> support for the old binding.
> 
[Pekon]: you map please ignore this one, as there is already a commit in 
your tree (omap-for-v3.11/gpmc) which does similar, therefore conflicting.
	Commit  f40739faba8e804cf46505869ab98ad7c4a88833 
	ARM: dts: OMAP2+: Simplify NAND support

I'll post separate patch for AM33xx DTB update for Benoit's tree.

Thanks..
with regards, pekon

Re: [PATCH 1/2] ARM: OMAP2+: gpmc: get number of useable GPMC chip-selects via DT

[Tony Lindgren]

* Gupta, Pekon <pekon@ti.com> [130531 05:07]:
> From: "Gupta, Pekon" <pekon@ti.com>
> 
> This patch enables usage of DT property 'gpmc,num-cs' as already documented in
> Documentation/devicetree/bindings/bus/ti-gpmc.txt
> 
> Though GPMC hardware supports upto 8 chip-selects, but all chip-selects may
> not be available for use because:
> - chip-select pin may not be bonded out at SoC device boundary.
> - chip-select pin-mux may conflict with other pins usage.
> - board level constrains.
> 
> gpmc,num-cs allows user to configure maximum number of GPMC chip-selects
> available for use on any given platform. This ensures:
> - GPMC child nodes having chip-selects within allowed range are only probed.
> - And un-used GPMC chip-selects remain blocked.(may be for security reasons).

Thanks applying this patch into omap-for-v3.11/gpmc.

Regards,

Tony