From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Chew Chiau Ee <chiaue.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Christian Ruppert
<christian.ruppert-ux6zf3SgZrrQT0dZR+AlfA@public.gmane.org>,
Mika Westerberg
<mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Subject: Re: [PATCH] i2c-designware: Manually set RESTART bit between messages
Date: Wed, 3 Jul 2013 22:15:11 +0200 [thread overview]
Message-ID: <20130703201510.GB2958@katana> (raw)
In-Reply-To: <1371798328-31931-1-git-send-email-chiaue.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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CCing Mika and Christian.
On Fri, Jun 21, 2013 at 03:05:28PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the
> Designware I2C controller doesn't generate RESTART unless user specifically
> requests it by setting RESTART bit in IC_DATA_CMD register.
>
> Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from hardware
> register, we must always manually set the restart bit between messages.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
How come restart has worked before? Or did it not?
> ---
> drivers/i2c/busses/i2c-designware-core.c | 14 ++++++++++++++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
> index 3de5494..9348439 100644
> --- a/drivers/i2c/busses/i2c-designware-core.c
> +++ b/drivers/i2c/busses/i2c-designware-core.c
> @@ -403,6 +403,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> u32 addr = msgs[dev->msg_write_idx].addr;
> u32 buf_len = dev->tx_buf_len;
> u8 *buf = dev->tx_buf;
> + bool need_restart = false;
>
> intr_mask = DW_IC_INTR_DEFAULT_MASK;
>
> @@ -430,6 +431,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> /* new i2c_msg */
> buf = msgs[dev->msg_write_idx].buf;
> buf_len = msgs[dev->msg_write_idx].len;
> +
> + /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
> + * IC_RESTART_EN are set, we must manually
> + * set restart bit between messages.
> + */
> + if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
> + (dev->msg_write_idx > 0))
> + need_restart = true;
> }
>
> tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
> @@ -448,6 +457,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> buf_len == 1)
> cmd |= BIT(9);
>
> + if (need_restart) {
> + cmd |= BIT(10);
> + need_restart = false;
> + }
> +
> if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
>
> /* avoid rx buffer overrun */
> --
> 1.7.4.4
>
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@the-dreams.de>
To: Chew Chiau Ee <chiaue.ee.chew@intel.com>
Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
Christian Ruppert <christian.ruppert@abilis.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH] i2c-designware: Manually set RESTART bit between messages
Date: Wed, 3 Jul 2013 22:15:11 +0200 [thread overview]
Message-ID: <20130703201510.GB2958@katana> (raw)
In-Reply-To: <1371798328-31931-1-git-send-email-chiaue.ee.chew@intel.com>
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CCing Mika and Christian.
On Fri, Jun 21, 2013 at 03:05:28PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the
> Designware I2C controller doesn't generate RESTART unless user specifically
> requests it by setting RESTART bit in IC_DATA_CMD register.
>
> Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from hardware
> register, we must always manually set the restart bit between messages.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
How come restart has worked before? Or did it not?
> ---
> drivers/i2c/busses/i2c-designware-core.c | 14 ++++++++++++++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
> index 3de5494..9348439 100644
> --- a/drivers/i2c/busses/i2c-designware-core.c
> +++ b/drivers/i2c/busses/i2c-designware-core.c
> @@ -403,6 +403,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> u32 addr = msgs[dev->msg_write_idx].addr;
> u32 buf_len = dev->tx_buf_len;
> u8 *buf = dev->tx_buf;
> + bool need_restart = false;
>
> intr_mask = DW_IC_INTR_DEFAULT_MASK;
>
> @@ -430,6 +431,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> /* new i2c_msg */
> buf = msgs[dev->msg_write_idx].buf;
> buf_len = msgs[dev->msg_write_idx].len;
> +
> + /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
> + * IC_RESTART_EN are set, we must manually
> + * set restart bit between messages.
> + */
> + if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
> + (dev->msg_write_idx > 0))
> + need_restart = true;
> }
>
> tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
> @@ -448,6 +457,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
> buf_len == 1)
> cmd |= BIT(9);
>
> + if (need_restart) {
> + cmd |= BIT(10);
> + need_restart = false;
> + }
> +
> if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
>
> /* avoid rx buffer overrun */
> --
> 1.7.4.4
>
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next prev parent reply other threads:[~2013-07-03 20:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-21 7:05 [PATCH] i2c-designware: Manually set RESTART bit between messages Chew Chiau Ee
2013-06-21 7:05 ` Chew Chiau Ee
[not found] ` <1371798328-31931-1-git-send-email-chiaue.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2013-07-03 20:15 ` Wolfram Sang [this message]
2013-07-03 20:15 ` Wolfram Sang
2013-07-04 7:41 ` Mika Westerberg
2013-07-04 7:41 ` Mika Westerberg
[not found] ` <20130704074121.GD4898-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2013-07-16 3:27 ` Chew, Chiau Ee
2013-07-16 3:27 ` Chew, Chiau Ee
2013-08-07 14:28 ` Wolfram Sang
2013-08-07 14:28 ` Wolfram Sang
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