Re: [PATCH] i2c: mxs: fix broken timing calculation

[Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>]

Dear Wolfram Sang,

> On Thu, Jul 18, 2013 at 01:18:48PM +0200, Lothar Waßmann wrote:
> > Hi,
> > 
> > > > Marek Vasut writes:
> > > > > > > btw offtopic, I will at least try to fix the PIO in the
> > > > > > > meantime.
> > > > > > 
> > > > > > Did you succeed at this? Because this is the real problem for the
> > > > > > DS1339 failing on our board. With DMA only transfers it works,
> > > > > > but other chips (TSC2007, PCA9554, SGTL5000) fail.
> > > > > 
> > > > > Is that correct to assume that even DMA fails? So far I got to a
> > > > > patch [1], which is almost an RFC, but please give it a go. I
> > > > > suspect I didn't CC you, I will CC you on V2.
> > > > 
> > > > I applied that patch and all the above mentioned devices seem to work
> > > > with it.
> > > > And with my patch the timing is also correct.
> > > 
> > > First, please accept my appology for the delay. I finally measured the
> > > bus. Without this patch, I see 107khz at 100kHz setting and 410kHz at
> > > 400kHz setting. With this patch I see 93kHz and 307kHz respectively.
> > > 
> > > I suspect the result really is board-dependent. Can you measure MX28EVK
> > > so we know what the result is there please? I don't have one here.
> > 
> > No, I don't have an EVK. Obviously the base clock from which the I2C
> > clock is derived must be different from 24MHz on your board.
> > 
> > Can you measure the high and low width of the SCL signal when setting
> > the HIGH_COUNT and LOW_COUNT to 1 and 10 (0x0a) successively?
> > 
> > I'm getting a LOW pulse with of:
> > 130ns, 520ns
> > and a HIGH pulse width of:
> > 330ns, 730ns
> > 
> > Thus the granularity of the timing setting is about 40ns which is
> > close the period of the 24MHz clock of 41.666ns that the SCL timing
> > generation is based on.
> 
> Ping, waiting for updates. Marek, any time for this?

I talked to Lothar OTR for a little, since the files with measurements were big. 
I think we can apply these as after this patch, the result on both M28EVK and 
MX23EVK is reasonably good.

Please add my Acked-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> and apply.

> Haven't checked in detail if it is a similar issue, yet the designware
> people had some in-depth discussions about I2C timings and PCB
> influences...

Yes, that's what I am a little worried as the results of my measurements 
slightly differ on both boards. Maybe we should mull over this stuff a little 
longer, thanks for bringing this up. On the other hand, the results seems close 
enough to not cause trouble.

Best regards,
Marek Vasut