[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padmavathi Venna]

This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
audio subsystem has a gate bit for ADMA controller and the some of the parent
clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
adds provision for supporting both the platforms by determining the parent clk
names based on compatible string.

Changes since V1:
	- parent clocks are determined by using the compatible string and not
	  passed via device tree as done in V1 because the probing order of
	  the clock providers can't be guaranteed.

Andrew Bresticker (3):
  clk: exynos-audss: add support for Exynos 5420
  clk: exynos-audss: set correct parent clocks
  ARM: dts: exynos5420: add audio clock controller

Padmavathi Venna (1):
  ARM: dts: Correct the /include entry on exynos5420 dtsi file

 .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
 arch/arm/boot/dts/exynos5420.dtsi                  |   11 ++++++++++-
 drivers/clk/samsung/clk-exynos-audss.c             |   20 +++++++++++++++++++-
 include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
 4 files changed, 36 insertions(+), 5 deletions(-)

-- 
1.7.4.4

[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padmavathi Venna]

This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
audio subsystem has a gate bit for ADMA controller and the some of the parent
clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
adds provision for supporting both the platforms by determining the parent clk
names based on compatible string.

Changes since V1:
	- parent clocks are determined by using the compatible string and not
	  passed via device tree as done in V1 because the probing order of
	  the clock providers can't be guaranteed.

Andrew Bresticker (3):
  clk: exynos-audss: add support for Exynos 5420
  clk: exynos-audss: set correct parent clocks
  ARM: dts: exynos5420: add audio clock controller

Padmavathi Venna (1):
  ARM: dts: Correct the /include entry on exynos5420 dtsi file

 .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
 arch/arm/boot/dts/exynos5420.dtsi                  |   11 ++++++++++-
 drivers/clk/samsung/clk-exynos-audss.c             |   20 +++++++++++++++++++-
 include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
 4 files changed, 36 insertions(+), 5 deletions(-)

-- 
1.7.4.4

[PATCH V1 1/4] clk: exynos-audss: add support for Exynos 5420

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
seviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
 drivers/clk/samsung/clk-exynos-audss.c             |    8 ++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a120180..3115930 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
 
 - compatible: should be one of the following:
   - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
-  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
-
+  - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+    SoCs.
+  - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+    SoCs.
 - reg: physical base address and length of the controller's register set.
 
 - #clock-cells: should be 1.
@@ -34,6 +36,7 @@ i2s_bus         6
 sclk_i2s        7
 pcm_bus         8
 sclk_pcm        9
+adma            10      Exynos5420
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..86d2606 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np)
 				"div_pcm0", CLK_SET_RATE_PARENT,
 				reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
+	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
+		clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 9, 0, &lock);
+	}
+
 #ifdef CONFIG_PM_SLEEP
 	register_syscore_ops(&exynos_audss_clk_syscore_ops);
 #endif
@@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
 		exynos_audss_clk_init);
 CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
 		exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5420_audss_clk, "samsung,exynos5420-audss-clock",
+		exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
 #define EXYNOS_SCLK_I2S	7
 #define EXYNOS_PCM_BUS		8
 #define EXYNOS_SCLK_PCM	9
+#define EXYNOS_ADMA		10
 
-#define EXYNOS_AUDSS_MAX_CLKS	10
+#define EXYNOS_AUDSS_MAX_CLKS	11
 
 #endif
-- 
1.7.4.4

[PATCH V1 1/4] clk: exynos-audss: add support for Exynos 5420

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
seviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
 drivers/clk/samsung/clk-exynos-audss.c             |    8 ++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a120180..3115930 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
 
 - compatible: should be one of the following:
   - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
-  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
-
+  - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+    SoCs.
+  - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+    SoCs.
 - reg: physical base address and length of the controller's register set.
 
 - #clock-cells: should be 1.
@@ -34,6 +36,7 @@ i2s_bus         6
 sclk_i2s        7
 pcm_bus         8
 sclk_pcm        9
+adma            10      Exynos5420
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..86d2606 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np)
 				"div_pcm0", CLK_SET_RATE_PARENT,
 				reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
+	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
+		clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 9, 0, &lock);
+	}
+
 #ifdef CONFIG_PM_SLEEP
 	register_syscore_ops(&exynos_audss_clk_syscore_ops);
 #endif
@@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
 		exynos_audss_clk_init);
 CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
 		exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5420_audss_clk, "samsung,exynos5420-audss-clock",
+		exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
 #define EXYNOS_SCLK_I2S	7
 #define EXYNOS_PCM_BUS		8
 #define EXYNOS_SCLK_PCM	9
+#define EXYNOS_ADMA		10
 
-#define EXYNOS_AUDSS_MAX_CLKS	10
+#define EXYNOS_AUDSS_MAX_CLKS	11
 
 #endif
-- 
1.7.4.4

[PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

Different Exynos SoCs have different names for certain input clocks
to the AudioSS block.  Since the order in which clock providers are
probed is not guaranteed, we can't use the device-tree to pass the
correct input clocks.  Instead, use the compatibility string to
determine what the correct parent clocks should be.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
 drivers/clk/samsung/clk-exynos-audss.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..d81c5f8 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
 /* list of all parent clock list */
 static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
 static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+static const char *sclk_pcm_p = "sclk_pcm0";
 
 #ifdef CONFIG_PM_SLEEP
 static int exynos_audss_clk_suspend(void)
@@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
 		return;
 	}
 
+	/* fix up clock parent names based on SoC */
+	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
+		mout_i2s_p[2] = "sclk_maudio0";
+		sclk_pcm_p = "sclk_maupcm0";
+	} else if (of_device_is_compatible(np,
+					"samsung,exynos5250-audss-clock")) {
+		sclk_pcm_p = "div_pcm0";
+	}
+
 	clk_data.clks = clk_table;
 	clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
@@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
 				reg_base + ASS_CLK_GATE, 4, 0, &lock);
 
 	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
-				"div_pcm0", CLK_SET_RATE_PARENT,
+				sclk_pcm_p, CLK_SET_RATE_PARENT,
 				reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
 	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
-- 
1.7.4.4

[PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

Different Exynos SoCs have different names for certain input clocks
to the AudioSS block.  Since the order in which clock providers are
probed is not guaranteed, we can't use the device-tree to pass the
correct input clocks.  Instead, use the compatibility string to
determine what the correct parent clocks should be.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
 drivers/clk/samsung/clk-exynos-audss.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..d81c5f8 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
 /* list of all parent clock list */
 static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
 static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+static const char *sclk_pcm_p = "sclk_pcm0";
 
 #ifdef CONFIG_PM_SLEEP
 static int exynos_audss_clk_suspend(void)
@@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
 		return;
 	}
 
+	/* fix up clock parent names based on SoC */
+	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
+		mout_i2s_p[2] = "sclk_maudio0";
+		sclk_pcm_p = "sclk_maupcm0";
+	} else if (of_device_is_compatible(np,
+					"samsung,exynos5250-audss-clock")) {
+		sclk_pcm_p = "div_pcm0";
+	}
+
 	clk_data.clks = clk_table;
 	clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
@@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
 				reg_base + ASS_CLK_GATE, 4, 0, &lock);
 
 	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
-				"div_pcm0", CLK_SET_RATE_PARENT,
+				sclk_pcm_p, CLK_SET_RATE_PARENT,
 				reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
 	if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
-- 
1.7.4.4

Re: [PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Mike Turquette]

Quoting Padmavathi Venna (2013-08-16 00:49:36)
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> Different Exynos SoCs have different names for certain input clocks
> to the AudioSS block.  Since the order in which clock providers are
> probed is not guaranteed, we can't use the device-tree to pass the
> correct input clocks.

Why not? Could your audss binding include something like a "clocks"
property with phandles to the input clocks? Then your audss clock driver
could just use clk_get like a regular driver to get the parents.

Regards,
Mike

> Instead, use the compatibility string to
> determine what the correct parent clocks should be.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> ---
>  drivers/clk/samsung/clk-exynos-audss.c |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> index 86d2606..d81c5f8 100644
> --- a/drivers/clk/samsung/clk-exynos-audss.c
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
>  /* list of all parent clock list */
>  static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>  static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
> +static const char *sclk_pcm_p = "sclk_pcm0";
>  
>  #ifdef CONFIG_PM_SLEEP
>  static int exynos_audss_clk_suspend(void)
> @@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
>                 return;
>         }
>  
> +       /* fix up clock parent names based on SoC */
> +       if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
> +               mout_i2s_p[2] = "sclk_maudio0";
> +               sclk_pcm_p = "sclk_maupcm0";
> +       } else if (of_device_is_compatible(np,
> +                                       "samsung,exynos5250-audss-clock")) {
> +               sclk_pcm_p = "div_pcm0";
> +       }
> +
>         clk_data.clks = clk_table;
>         clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
>         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> @@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
>                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
>  
>         clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> -                               "div_pcm0", CLK_SET_RATE_PARENT,
> +                               sclk_pcm_p, CLK_SET_RATE_PARENT,
>                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
>  
>         if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
> -- 
> 1.7.4.4

[PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Mike Turquette]

Quoting Padmavathi Venna (2013-08-16 00:49:36)
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> Different Exynos SoCs have different names for certain input clocks
> to the AudioSS block.  Since the order in which clock providers are
> probed is not guaranteed, we can't use the device-tree to pass the
> correct input clocks.

Why not? Could your audss binding include something like a "clocks"
property with phandles to the input clocks? Then your audss clock driver
could just use clk_get like a regular driver to get the parents.

Regards,
Mike

> Instead, use the compatibility string to
> determine what the correct parent clocks should be.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> ---
>  drivers/clk/samsung/clk-exynos-audss.c |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> index 86d2606..d81c5f8 100644
> --- a/drivers/clk/samsung/clk-exynos-audss.c
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
>  /* list of all parent clock list */
>  static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>  static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
> +static const char *sclk_pcm_p = "sclk_pcm0";
>  
>  #ifdef CONFIG_PM_SLEEP
>  static int exynos_audss_clk_suspend(void)
> @@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
>                 return;
>         }
>  
> +       /* fix up clock parent names based on SoC */
> +       if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
> +               mout_i2s_p[2] = "sclk_maudio0";
> +               sclk_pcm_p = "sclk_maupcm0";
> +       } else if (of_device_is_compatible(np,
> +                                       "samsung,exynos5250-audss-clock")) {
> +               sclk_pcm_p = "div_pcm0";
> +       }
> +
>         clk_data.clks = clk_table;
>         clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
>         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> @@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
>                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
>  
>         clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> -                               "div_pcm0", CLK_SET_RATE_PARENT,
> +                               sclk_pcm_p, CLK_SET_RATE_PARENT,
>                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
>  
>         if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
> -- 
> 1.7.4.4

Re: [PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Tomasz Figa]

On Tuesday 27 of August 2013 17:43:41 Mike Turquette wrote:
> Quoting Padmavathi Venna (2013-08-16 00:49:36)
> 
> > From: Andrew Bresticker <abrestic@chromium.org>
> > 
> > Different Exynos SoCs have different names for certain input clocks
> > to the AudioSS block.  Since the order in which clock providers are
> > probed is not guaranteed, we can't use the device-tree to pass the
> > correct input clocks.
> 
> Why not? Could your audss binding include something like a "clocks"
> property with phandles to the input clocks? Then your audss clock driver
> could just use clk_get like a regular driver to get the parents.

AFAIR, the driver is currently probed using of_clk_init(), so the reason 
was probably being unable to defer probing.

However this is not the core system clock controller, so I believe there 
is no reason for it not to be a normal platform driver.

Best regards,
Tomasz

[PATCH V2 2/4] clk: exynos-audss: set correct parent clocks

[Tomasz Figa]

On Tuesday 27 of August 2013 17:43:41 Mike Turquette wrote:
> Quoting Padmavathi Venna (2013-08-16 00:49:36)
> 
> > From: Andrew Bresticker <abrestic@chromium.org>
> > 
> > Different Exynos SoCs have different names for certain input clocks
> > to the AudioSS block.  Since the order in which clock providers are
> > probed is not guaranteed, we can't use the device-tree to pass the
> > correct input clocks.
> 
> Why not? Could your audss binding include something like a "clocks"
> property with phandles to the input clocks? Then your audss clock driver
> could just use clk_get like a regular driver to get the parents.

AFAIR, the driver is currently probed using of_clk_init(), so the reason 
was probably being unable to defer probing.

However this is not the core system clock controller, so I believe there 
is no reason for it not to be a normal platform driver.

Best regards,
Tomasz

[PATCH V2 3/4] ARM: dts: Correct the /include entry on exynos5420 dtsi file

[Padmavathi Venna]

This patch corrects the /include to #include on exynos5420

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..334f7b7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,7 @@
  */
 
 #include "exynos5.dtsi"
-/include/ "exynos5420-pinctrl.dtsi"
+#include "exynos5420-pinctrl.dtsi"
 / {
 	compatible = "samsung,exynos5420";
 
-- 
1.7.4.4

[PATCH V2 3/4] ARM: dts: Correct the /include entry on exynos5420 dtsi file

[Padmavathi Venna]

This patch corrects the /include to #include on exynos5420

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..334f7b7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,7 @@
  */
 
 #include "exynos5.dtsi"
-/include/ "exynos5420-pinctrl.dtsi"
+#include "exynos5420-pinctrl.dtsi"
 / {
 	compatible = "samsung,exynos5420";
 
-- 
1.7.4.4

[PATCH V2 4/4] ARM: dts: exynos5420: add audio clock controller

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 334f7b7..dde4cc2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -15,6 +15,9 @@
 
 #include "exynos5.dtsi"
 #include "exynos5420-pinctrl.dtsi"
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5420";
 
@@ -65,6 +68,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller@3810000 {
+		compatible = "samsung,exynos5420-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	mct@101C0000 {
 		compatible = "samsung,exynos4210-mct";
 		reg = <0x101C0000 0x800>;
-- 
1.7.4.4

[PATCH V2 4/4] ARM: dts: exynos5420: add audio clock controller

[Padmavathi Venna]

From: Andrew Bresticker <abrestic@chromium.org>

This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 334f7b7..dde4cc2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -15,6 +15,9 @@
 
 #include "exynos5.dtsi"
 #include "exynos5420-pinctrl.dtsi"
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5420";
 
@@ -65,6 +68,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller at 3810000 {
+		compatible = "samsung,exynos5420-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	mct at 101C0000 {
 		compatible = "samsung,exynos4210-mct";
 		reg = <0x101C0000 0x800>;
-- 
1.7.4.4

Re: [PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padma Venkat]

Hi Mike,

On Fri, Aug 16, 2013 at 1:19 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
> This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
> audio subsystem has a gate bit for ADMA controller and the some of the parent
> clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
> adds provision for supporting both the platforms by determining the parent clk
> names based on compatible string.
>
> Changes since V1:
>         - parent clocks are determined by using the compatible string and not
>           passed via device tree as done in V1 because the probing order of
>           the clock providers can't be guaranteed.
>
> Andrew Bresticker (3):
>   clk: exynos-audss: add support for Exynos 5420
>   clk: exynos-audss: set correct parent clocks

Can you apply the above two patches into your tree?

>   ARM: dts: exynos5420: add audio clock controller
>
> Padmavathi Venna (1):
>   ARM: dts: Correct the /include entry on exynos5420 dtsi file
>
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
>  arch/arm/boot/dts/exynos5420.dtsi                  |   11 ++++++++++-
>  drivers/clk/samsung/clk-exynos-audss.c             |   20 +++++++++++++++++++-
>  include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
>  4 files changed, 36 insertions(+), 5 deletions(-)
>
> --
> 1.7.4.4
>

Thanks
Padma

[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padma Venkat]

Hi Mike,

On Fri, Aug 16, 2013 at 1:19 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
> This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
> audio subsystem has a gate bit for ADMA controller and the some of the parent
> clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
> adds provision for supporting both the platforms by determining the parent clk
> names based on compatible string.
>
> Changes since V1:
>         - parent clocks are determined by using the compatible string and not
>           passed via device tree as done in V1 because the probing order of
>           the clock providers can't be guaranteed.
>
> Andrew Bresticker (3):
>   clk: exynos-audss: add support for Exynos 5420
>   clk: exynos-audss: set correct parent clocks

Can you apply the above two patches into your tree?

>   ARM: dts: exynos5420: add audio clock controller
>
> Padmavathi Venna (1):
>   ARM: dts: Correct the /include entry on exynos5420 dtsi file
>
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
>  arch/arm/boot/dts/exynos5420.dtsi                  |   11 ++++++++++-
>  drivers/clk/samsung/clk-exynos-audss.c             |   20 +++++++++++++++++++-
>  include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
>  4 files changed, 36 insertions(+), 5 deletions(-)
>
> --
> 1.7.4.4
>

Thanks
Padma

Re: [PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padma Venkat]

Hi Mike,

On Mon, Aug 19, 2013 at 2:18 PM, Padma Venkat <padma.kvr@gmail.com> wrote:
> Hi Mike,
>
> On Fri, Aug 16, 2013 at 1:19 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
>> This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
>> audio subsystem has a gate bit for ADMA controller and the some of the parent
>> clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
>> adds provision for supporting both the platforms by determining the parent clk
>> names based on compatible string.
>>
>> Changes since V1:
>>         - parent clocks are determined by using the compatible string and not
>>           passed via device tree as done in V1 because the probing order of
>>           the clock providers can't be guaranteed.
>>
>> Andrew Bresticker (3):
>>   clk: exynos-audss: add support for Exynos 5420
>>   clk: exynos-audss: set correct parent clocks
>
> Can you apply the above two patches into your tree?
>

If there is no review comment on the above two can you please
acknowledge them? The below patch is dependent on these two patches
and Kukjin is waiting for these patches to be merged.

[V2] ARM: dts: Add DMA controller node info on Exynos5420.
https://patchwork.kernel.org/patch/2844436/

Thanks
Padma

[PATCH V2 0/4] clk: Samsung: audss: Add support for Exynos5420

[Padma Venkat]

Hi Mike,

On Mon, Aug 19, 2013 at 2:18 PM, Padma Venkat <padma.kvr@gmail.com> wrote:
> Hi Mike,
>
> On Fri, Aug 16, 2013 at 1:19 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
>> This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420
>> audio subsystem has a gate bit for ADMA controller and the some of the parent
>> clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch
>> adds provision for supporting both the platforms by determining the parent clk
>> names based on compatible string.
>>
>> Changes since V1:
>>         - parent clocks are determined by using the compatible string and not
>>           passed via device tree as done in V1 because the probing order of
>>           the clock providers can't be guaranteed.
>>
>> Andrew Bresticker (3):
>>   clk: exynos-audss: add support for Exynos 5420
>>   clk: exynos-audss: set correct parent clocks
>
> Can you apply the above two patches into your tree?
>

If there is no review comment on the above two can you please
acknowledge them? The below patch is dependent on these two patches
and Kukjin is waiting for these patches to be merged.

[V2] ARM: dts: Add DMA controller node info on Exynos5420.
https://patchwork.kernel.org/patch/2844436/

Thanks
Padma