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From: Andi Kleen <ak@linux.intel.com>
To: Vince Weaver <vince@deater.net>
Cc: Andi Kleen <andi@firstfloor.org>,
	mingo@elte.hu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2
Date: Wed, 4 Sep 2013 10:05:01 -0700	[thread overview]
Message-ID: <20130904170501.GL16724@tassilo.jf.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1309041015130.28706@pianoman.cluster.toy>

On Wed, Sep 04, 2013 at 10:21:27AM -0400, Vince Weaver wrote:
> On Wed, 4 Sep 2013, Andi Kleen wrote:
> 
> > > What does this mean?  The above values are exported as part of 
> > >   include/uapi/linux/perf_event.h
> > > Do they not work yet?
> > 
> > You can filter on the fields, but you can't see them outside
> > the kernel driver yet.  The patch to see them is still pending.
> 
> so you can filter for aborts, but they'll never show up in the lbr[]
> sample buffer?

They will show up, you just don't know that they are aborts 
because the two new status bits are not exported.

> 
> > > > >  What happens if you set both in transaction and not in?
> > > > 
> > > > Then you get all branches.
> > > 
> > > so what happens if you set neither "PERF_SAMPLE_BRANCH_IN_TX" nor
> > > "PERF_SAMPLE_BRANCH_NO_TX"?  Logically you'd get no branches at all,
> > > but that can't be true as all code prior to 3.11 didn't set those values.
> > 
> > Then you get all branches too
> > 
> > (that's how all the other filters work too)
> 
> This is a really confusing API
> 
> so does setting "PERF_SAMPLE_BRANCH_ANY" also enable all of the TX types?
> 
> Is leaving branch_sample_type at 0 the same as setting it to all 1s?

I believe so.

It may be also that the catch all only works if everything is 0.

-Andi
-- 
ak@linux.intel.com -- Speaking for myself only

  reply	other threads:[~2013-09-04 17:05 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-20 19:06 Basic perf PMU support for Haswell v11 Andi Kleen
2013-04-20 19:06 ` [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5 Andi Kleen
2013-04-20 19:06 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v8 Andi Kleen
2013-04-20 19:06 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS support v4 Andi Kleen
2013-04-20 19:06 ` [PATCH 4/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-04-20 19:06 ` [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2 Andi Kleen
2013-09-03 19:25   ` Vince Weaver
2013-09-03 20:28     ` Andi Kleen
2013-09-03 21:14       ` Vince Weaver
2013-09-03 22:37         ` Andi Kleen
2013-09-04 14:21           ` Vince Weaver
2013-09-04 17:05             ` Andi Kleen [this message]
2013-04-26  6:55 ` Basic perf PMU support for Haswell v11 Ingo Molnar
2013-04-26  6:59   ` Ingo Molnar
2013-05-01 10:48     ` Ingo Molnar
2013-04-26 22:52   ` Andi Kleen
2013-05-01 10:10     ` Your action on perf bug report is requested was " Andi Kleen
2013-05-01 10:33       ` Ingo Molnar
2013-05-02  8:38     ` Ingo Molnar
2013-05-02  8:49 ` Ingo Molnar

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