From: Shawn Guo <shawn.guo@linaro.org>
To: Dong Aisheng <b29396@freescale.com>
Cc: linux-mmc@vger.kernel.org, cjb@laptop.org, anton@enomsg.org,
linux-arm-kernel@lists.infradead.org, s.hauer@pengutronix.de
Subject: Re: [PATCH 8/8] ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3
Date: Thu, 5 Sep 2013 14:43:13 +0800 [thread overview]
Message-ID: <20130905064311.GE775@shlinux1.ap.freescale.net> (raw)
In-Reply-To: <1378299257-2980-9-git-send-email-b29396@freescale.com>
On Wed, Sep 04, 2013 at 08:54:17PM +0800, Dong Aisheng wrote:
> This is needed for supporting ultra high speed cards like SD3.0 cards.
>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> ---
> arch/arm/boot/dts/imx6dl.dtsi | 33 ++++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx6q.dtsi | 33 ++++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++-
> 3 files changed, 69 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 2b3ecd6..e983b81 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -203,6 +203,39 @@
> MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_3: usdhc3grp-3 { /* 100Mhz */
> + fsl,pins = <
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x170B9
> + MX6DL_PAD_SD3_CLK__SD3_CLK 0x100B9
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
> + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
> + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
> + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
> + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
> + MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
The patch needs to be rebased on my for-next, or linux-next or v3.12-rc1
(to be available). Also please use lowercase for hex values.
Shawn
> + >;
> + };
> +
> + pinctrl_usdhc3_4: usdhc3grp-4 { /* 200Mhz */
> + fsl,pins = <
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x170F9
> + MX6DL_PAD_SD3_CLK__SD3_CLK 0x100F9
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
> + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
> + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
> + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
> + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
> + MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> };
>
> weim {
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ba09dc3..a63b623 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -337,6 +337,39 @@
> MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_3: usdhc3grp-3 { /* 100Mhz */
> + fsl,pins = <
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x170B9
> + MX6Q_PAD_SD3_CLK__SD3_CLK 0x100B9
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x170B9
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x170B9
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x170B9
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x170B9
> + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x170B9
> + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x170B9
> + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x170B9
> + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x170B9
> + MX6Q_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_4: usdhc3grp-4 { /* 200Mhz */
> + fsl,pins = <
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x170F9
> + MX6Q_PAD_SD3_CLK__SD3_CLK 0x100F9
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x170F9
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x170F9
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x170F9
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x170F9
> + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x170F9
> + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x170F9
> + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x170F9
> + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x170F9
> + MX6Q_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> };
>
> usdhc4 {
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index e994011..c2c4d85 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -52,8 +52,10 @@
> };
>
> &usdhc3 {
> - pinctrl-names = "default";
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc3_1>;
> + pinctrl-1 = <&pinctrl_usdhc3_3>;
> + pinctrl-2 = <&pinctrl_usdhc3_4>;
> cd-gpios = <&gpio6 15 0>;
> wp-gpios = <&gpio1 13 0>;
> status = "okay";
> --
> 1.7.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: shawn.guo@linaro.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 8/8] ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3
Date: Thu, 5 Sep 2013 14:43:13 +0800 [thread overview]
Message-ID: <20130905064311.GE775@shlinux1.ap.freescale.net> (raw)
In-Reply-To: <1378299257-2980-9-git-send-email-b29396@freescale.com>
On Wed, Sep 04, 2013 at 08:54:17PM +0800, Dong Aisheng wrote:
> This is needed for supporting ultra high speed cards like SD3.0 cards.
>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> ---
> arch/arm/boot/dts/imx6dl.dtsi | 33 ++++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx6q.dtsi | 33 ++++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++-
> 3 files changed, 69 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 2b3ecd6..e983b81 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -203,6 +203,39 @@
> MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_3: usdhc3grp-3 { /* 100Mhz */
> + fsl,pins = <
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x170B9
> + MX6DL_PAD_SD3_CLK__SD3_CLK 0x100B9
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
> + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
> + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
> + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
> + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
> + MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
The patch needs to be rebased on my for-next, or linux-next or v3.12-rc1
(to be available). Also please use lowercase for hex values.
Shawn
> + >;
> + };
> +
> + pinctrl_usdhc3_4: usdhc3grp-4 { /* 200Mhz */
> + fsl,pins = <
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x170F9
> + MX6DL_PAD_SD3_CLK__SD3_CLK 0x100F9
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
> + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
> + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
> + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
> + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
> + MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> };
>
> weim {
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ba09dc3..a63b623 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -337,6 +337,39 @@
> MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_3: usdhc3grp-3 { /* 100Mhz */
> + fsl,pins = <
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x170B9
> + MX6Q_PAD_SD3_CLK__SD3_CLK 0x100B9
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x170B9
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x170B9
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x170B9
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x170B9
> + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x170B9
> + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x170B9
> + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x170B9
> + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x170B9
> + MX6Q_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_4: usdhc3grp-4 { /* 200Mhz */
> + fsl,pins = <
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x170F9
> + MX6Q_PAD_SD3_CLK__SD3_CLK 0x100F9
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x170F9
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x170F9
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x170F9
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x170F9
> + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x170F9
> + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x170F9
> + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x170F9
> + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x170F9
> + MX6Q_PAD_GPIO_18__SD3_VSELECT 0x17059
> + >;
> + };
> +
> };
>
> usdhc4 {
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index e994011..c2c4d85 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -52,8 +52,10 @@
> };
>
> &usdhc3 {
> - pinctrl-names = "default";
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc3_1>;
> + pinctrl-1 = <&pinctrl_usdhc3_3>;
> + pinctrl-2 = <&pinctrl_usdhc3_4>;
> cd-gpios = <&gpio6 15 0>;
> wp-gpios = <&gpio1 13 0>;
> status = "okay";
> --
> 1.7.1
>
>
next prev parent reply other threads:[~2013-09-05 6:44 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-04 12:54 [PATCH 0/8] mmc: sdhci-esdhc-imx: add SD3.0 support Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 1/8] mmc: sdhci: add hooks for platform specific tuning Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-05 3:14 ` Shawn Guo
2013-09-05 3:14 ` Shawn Guo
2013-09-05 14:53 ` Dong Aisheng
2013-09-05 14:53 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 2/8] mmc: sdhci: allow platform access of sdhci_send_command Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 3/8] sdhci: sdhci-esdhc-imx: support real clock on and off for imx6q Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-05 4:32 ` Shawn Guo
2013-09-05 4:32 ` Shawn Guo
2013-09-05 14:59 ` Dong Aisheng
2013-09-05 14:59 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 4/8] sdhci: sdhci-esdhci-imx: add sd3.0 clock tuning support Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-05 6:00 ` Shawn Guo
2013-09-05 6:00 ` Shawn Guo
2013-09-05 15:02 ` Dong Aisheng
2013-09-05 15:02 ` Dong Aisheng
2013-09-05 7:33 ` Ulf Hansson
2013-09-05 7:33 ` Ulf Hansson
2013-09-05 17:52 ` Dong Aisheng
2013-09-05 17:52 ` Dong Aisheng
2013-09-16 7:48 ` Ulf Hansson
2013-09-16 7:48 ` Ulf Hansson
2013-09-04 12:54 ` [PATCH 5/8] sdhci: sdhci-esdhc-imx: change pinctrl state according to uhs mode Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-05 6:34 ` Shawn Guo
2013-09-05 6:34 ` Shawn Guo
2013-09-05 15:06 ` Dong Aisheng
2013-09-05 15:06 ` Dong Aisheng
2013-09-05 7:38 ` Ulf Hansson
2013-09-05 7:38 ` Ulf Hansson
2013-09-05 16:04 ` Dong Aisheng
2013-09-05 16:04 ` Dong Aisheng
2013-09-13 14:01 ` Ulf Hansson
2013-09-13 14:01 ` Ulf Hansson
2013-09-13 16:38 ` Dong Aisheng
2013-09-13 16:38 ` Dong Aisheng
2013-09-05 18:40 ` Matt Sealey
2013-09-05 18:40 ` Matt Sealey
2013-09-11 9:26 ` Dong Aisheng
2013-09-11 9:26 ` Dong Aisheng
2013-09-27 0:28 ` Matt Sealey
2013-09-27 0:28 ` Matt Sealey
2013-09-04 12:54 ` [PATCH 6/8] mmc: sdhci-esdhc: correct pre_div for imx6q Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 7/8] mmc: sdhci-esdhc: set actual_clock in clock setting Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-04 12:54 ` [PATCH 8/8] ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3 Dong Aisheng
2013-09-04 12:54 ` Dong Aisheng
2013-09-05 6:43 ` Shawn Guo [this message]
2013-09-05 6:43 ` Shawn Guo
2013-09-05 15:09 ` Dong Aisheng
2013-09-05 15:09 ` Dong Aisheng
2013-09-05 8:03 ` Sascha Hauer
2013-09-05 8:03 ` Sascha Hauer
2013-09-05 15:29 ` Dong Aisheng
2013-09-05 15:29 ` Dong Aisheng
2013-09-05 7:42 ` [PATCH 0/8] mmc: sdhci-esdhc-imx: add SD3.0 support Ulf Hansson
2013-09-05 7:42 ` Ulf Hansson
2013-09-05 18:01 ` Dong Aisheng
2013-09-05 18:01 ` Dong Aisheng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20130905064311.GE775@shlinux1.ap.freescale.net \
--to=shawn.guo@linaro.org \
--cc=anton@enomsg.org \
--cc=b29396@freescale.com \
--cc=cjb@laptop.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-mmc@vger.kernel.org \
--cc=s.hauer@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.