[Qemu-devel] [PATCH v5 0/3] pci: partially implement master abort protocol

[Qemu-devel] [PATCH v5 0/3] pci: partially implement master abort protocol

[Marcel Apfelbaum]

PCI spec requires that a transaction that has not been claimed
by any PCI bus devices will be terminated by the initiator
with "master abort". For read transactions -1(FFFFFFFF) is returned and 
writes are silently dropped.

Implementation:
 - Allowed the MemoryRegion priority to be negative so a subregion will be
   visible on all the addresses not covered by other container subregions.
 - Added a memory region with negative priority that extends over all the
   pci address space. This region catches all the accesses
   to the unassigned pci addresses.
 - The MemoryRegion's ops emulates the master abort scenario.

I am working on implementing the following on top of this series
 - Implement upstream master abort
 - Handling of RECEIVED MASTER ABORT BIT in Status register

Changes from v4:
 - Addressed Peter Maydell comments
   - Changed memory patches commit comment
 - Addressed Michael S. Tsirkin comments
   - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN

Changes from v3:
 - Addressed Peter Maydell comments
   - Removed unnecessary changes to priority of MemoryListener
   - Ensured that priority is now signed in all related places
   - Added to memory docs explanation on signed priorities
 - Addresses Michael S. Tsirkin comments
   - Changed the name of the new Memory region to master_abort_mem
   - Made master abort priority INT_MIN instead of -1
 - Removed handling of RECEIVED MASTER ABORT BIT; it will be taken
   care in a different series

Changes from v2:
 - minor: changed nr of patches in the title
 - minor: modified series list

Changes from v1:
 - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on
    various Host Bridges
 - "pci-unassgined-mem" does not have a ".valid.accept" field and
    implements read write methods

Marcel Apfelbaum (3):
  memory: Change MemoryRegion priorities from unsigned to signed
  docs/memory: Explictly state that MemoryRegion priority is signed
  hw/pci: partially handle pci master abort

 docs/memory.txt          |  4 ++++
 hw/core/sysbus.c         |  4 ++--
 hw/pci/pci.c             | 27 +++++++++++++++++++++++++++
 include/exec/memory.h    |  4 ++--
 include/hw/pci/pci_bus.h |  1 +
 include/hw/sysbus.h      |  2 +-
 memory.c                 |  4 ++--
 7 files changed, 39 insertions(+), 7 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH v5 1/3] memory: Change MemoryRegion priorities from unsigned to signed

[Marcel Apfelbaum]

When memory regions overlap, priority can be used to specify
which of them takes priority. By making the priority values signed
rather than unsigned, we make it more convenient to implement
a situation where one "background" region should appear only
where no other region exists: rather than having to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
---
Changes from v4:
 - Addressed Peter Maydell comments
   - Changed commit comment

Changes from v3:
 - Addressed Peter Maydell comments
   - Removed unnecessary changes to priority of MemoryListener
   - Ensured that priority is now signed in all related places

 hw/core/sysbus.c      | 4 ++--
 include/exec/memory.h | 4 ++--
 include/hw/sysbus.h   | 2 +-
 memory.c              | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index b84cd4a..146f50a 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -49,7 +49,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq)
 }
 
 static void sysbus_mmio_map_common(SysBusDevice *dev, int n, hwaddr addr,
-                                   bool may_overlap, unsigned priority)
+                                   bool may_overlap, int priority)
 {
     assert(n >= 0 && n < dev->num_mmio);
 
@@ -81,7 +81,7 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
 }
 
 void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
-                             unsigned priority)
+                             int priority)
 {
     sysbus_mmio_map_common(dev, n, addr, true, priority);
 }
diff --git a/include/exec/memory.h b/include/exec/memory.h
index ebe0d24..480dfbf 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -153,7 +153,7 @@ struct MemoryRegion {
     bool flush_coalesced_mmio;
     MemoryRegion *alias;
     hwaddr alias_offset;
-    unsigned priority;
+    int priority;
     bool may_overlap;
     QTAILQ_HEAD(subregions, MemoryRegion) subregions;
     QTAILQ_ENTRY(MemoryRegion) subregions_link;
@@ -779,7 +779,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
 void memory_region_add_subregion_overlap(MemoryRegion *mr,
                                          hwaddr offset,
                                          MemoryRegion *subregion,
-                                         unsigned priority);
+                                         int priority);
 
 /**
  * memory_region_get_ram_addr: Get the ram address associated with a memory
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
index bb50a87..f5aaa05 100644
--- a/include/hw/sysbus.h
+++ b/include/hw/sysbus.h
@@ -68,7 +68,7 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
 void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
 void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
 void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
-                             unsigned priority);
+                             int priority);
 void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
                    MemoryRegion *mem);
 void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
diff --git a/memory.c b/memory.c
index 5a10fd0..f49d31a 100644
--- a/memory.c
+++ b/memory.c
@@ -1473,7 +1473,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
 void memory_region_add_subregion_overlap(MemoryRegion *mr,
                                          hwaddr offset,
                                          MemoryRegion *subregion,
-                                         unsigned priority)
+                                         int priority)
 {
     subregion->may_overlap = true;
     subregion->priority = priority;
@@ -1506,7 +1506,7 @@ void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
 {
     MemoryRegion *parent = mr->parent;
-    unsigned priority = mr->priority;
+    int priority = mr->priority;
     bool may_overlap = mr->may_overlap;
 
     if (addr == mr->addr || !parent) {
-- 
1.8.3.1

[Qemu-devel] [PATCH v5 2/3] docs/memory: Explictly state that MemoryRegion priority is signed

[Marcel Apfelbaum]

When memory regions overlap, priority can be used to specify
which of them takes priority. By making the priority values signed
rather than unsigned, we make it more convenient to implement
a situation where one "background" region should appear only
where no other region exists: rather than having to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
---
Changes from v4:
 - Addressed Peter Maydell comments
   - Changed commit comment
  docs/memory.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/memory.txt b/docs/memory.txt
index feb9fe9..174c0d7 100644
--- a/docs/memory.txt
+++ b/docs/memory.txt
@@ -80,6 +80,10 @@ guest.  This is done with memory_region_add_subregion_overlap(), which
 allows the region to overlap any other region in the same container, and
 specifies a priority that allows the core to decide which of two regions at
 the same address are visible (highest wins).
+Priority values are signed, and the default value is zero. This means that
+you can use memory_region_add_subregion_overlap() both to specify a region
+that must sit 'above' any others (with a positive priority) and also a
+background region that sits 'below' others (with a negative priority).
 
 Visibility
 ----------
-- 
1.8.3.1

[Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort

[Marcel Apfelbaum]

A MemoryRegion with negative priority was created and
it spans over all the pci address space.
It "intercepts" the accesses to unassigned pci
address space and will follow the pci spec:
 1. returns -1 on read
 2. does nothing on write

Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
      of the device that initiated the transaction will be
      implemented in another series

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
---
Changes from v4:
 - Addressed Michael S. Tsirkin comments
   - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
 - Fixed: overlap master_abort_mem at offset 0, not at
          bus->address_space_mem.addr

 hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
 include/hw/pci/pci_bus.h |  1 +
 2 files changed, 27 insertions(+)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ad1c1ca..d8a1b11 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
     return rootbus->qbus.name;
 }
 
+static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+   return -1ULL;
+}
+
+static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
+                                   unsigned size)
+{
+}
+
+static const MemoryRegionOps master_abort_mem_ops = {
+    .read = master_abort_mem_read,
+    .write = master_abort_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+#define MASTER_ABORT_MEM_PRIORITY INT_MIN
+
 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
@@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
     bus->address_space_mem = address_space_mem;
     bus->address_space_io = address_space_io;
 
+
+    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
+                          &master_abort_mem_ops, bus, "pci-master-abort",
+                          memory_region_size(bus->address_space_mem));
+    memory_region_add_subregion_overlap(bus->address_space_mem,
+                                        0, &bus->master_abort_mem,
+                                        MASTER_ABORT_MEM_PRIORITY);
+
     /* host bridge */
     QLIST_INIT(&bus->child);
 
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 9df1788..2ad5edb 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -23,6 +23,7 @@ struct PCIBus {
     PCIDevice *parent_dev;
     MemoryRegion *address_space_mem;
     MemoryRegion *address_space_io;
+    MemoryRegion master_abort_mem;
 
     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort

[Michael S. Tsirkin]

On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
> A MemoryRegion with negative priority was created and
> it spans over all the pci address space.
> It "intercepts" the accesses to unassigned pci
> address space and will follow the pci spec:
>  1. returns -1 on read
>  2. does nothing on write
> 
> Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
>       of the device that initiated the transaction will be
>       implemented in another series
> 
> Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
> ---
> Changes from v4:
>  - Addressed Michael S. Tsirkin comments
>    - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
>  - Fixed: overlap master_abort_mem at offset 0, not at
>           bus->address_space_mem.addr
> 
>  hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
>  include/hw/pci/pci_bus.h |  1 +
>  2 files changed, 27 insertions(+)
> 
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index ad1c1ca..d8a1b11 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
>      return rootbus->qbus.name;
>  }
>  
> +static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +   return -1ULL;
> +}
> +
> +static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
> +                                   unsigned size)
> +{
> +}
> +
> +static const MemoryRegionOps master_abort_mem_ops = {
> +    .read = master_abort_mem_read,
> +    .write = master_abort_mem_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +#define MASTER_ABORT_MEM_PRIORITY INT_MIN
> +
>  static void pci_bus_init(PCIBus *bus, DeviceState *parent,
>                           const char *name,
>                           MemoryRegion *address_space_mem,
> @@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
>      bus->address_space_mem = address_space_mem;
>      bus->address_space_io = address_space_io;
>  
> +
> +    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
> +                          &master_abort_mem_ops, bus, "pci-master-abort",
> +                          memory_region_size(bus->address_space_mem));
> +    memory_region_add_subregion_overlap(bus->address_space_mem,
> +                                        0, &bus->master_abort_mem,
> +                                        MASTER_ABORT_MEM_PRIORITY);
> +
>      /* host bridge */
>      QLIST_INIT(&bus->child);
>  

Does this handle devices behind bridges?


> diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> index 9df1788..2ad5edb 100644
> --- a/include/hw/pci/pci_bus.h
> +++ b/include/hw/pci/pci_bus.h
> @@ -23,6 +23,7 @@ struct PCIBus {
>      PCIDevice *parent_dev;
>      MemoryRegion *address_space_mem;
>      MemoryRegion *address_space_io;
> +    MemoryRegion master_abort_mem;
>  

Looks like this field is left uninitialized for bridge
devices (they don't seem to call pci_bus_init)?

>      QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
>      QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> -- 
> 1.8.3.1

Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort

[Marcel Apfelbaum]

On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
> > A MemoryRegion with negative priority was created and
> > it spans over all the pci address space.
> > It "intercepts" the accesses to unassigned pci
> > address space and will follow the pci spec:
> >  1. returns -1 on read
> >  2. does nothing on write
> > 
> > Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
> >       of the device that initiated the transaction will be
> >       implemented in another series
> > 
> > Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
> > ---
> > Changes from v4:
> >  - Addressed Michael S. Tsirkin comments
> >    - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
> >  - Fixed: overlap master_abort_mem at offset 0, not at
> >           bus->address_space_mem.addr
> > 
> >  hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
> >  include/hw/pci/pci_bus.h |  1 +
> >  2 files changed, 27 insertions(+)
> > 
> > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > index ad1c1ca..d8a1b11 100644
> > --- a/hw/pci/pci.c
> > +++ b/hw/pci/pci.c
> > @@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
> >      return rootbus->qbus.name;
> >  }
> >  
> > +static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > +   return -1ULL;
> > +}
> > +
> > +static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
> > +                                   unsigned size)
> > +{
> > +}
> > +
> > +static const MemoryRegionOps master_abort_mem_ops = {
> > +    .read = master_abort_mem_read,
> > +    .write = master_abort_mem_write,
> > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > +};
> > +
> > +#define MASTER_ABORT_MEM_PRIORITY INT_MIN
> > +
> >  static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> >                           const char *name,
> >                           MemoryRegion *address_space_mem,
> > @@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> >      bus->address_space_mem = address_space_mem;
> >      bus->address_space_io = address_space_io;
> >  
> > +
> > +    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
> > +                          &master_abort_mem_ops, bus, "pci-master-abort",
> > +                          memory_region_size(bus->address_space_mem));
> > +    memory_region_add_subregion_overlap(bus->address_space_mem,
> > +                                        0, &bus->master_abort_mem,
> > +                                        MASTER_ABORT_MEM_PRIORITY);
> > +
> >      /* host bridge */
> >      QLIST_INIT(&bus->child);
> >  
> 
> Does this handle devices behind bridges?
Yes, tested also for devices behind bridge.

> 
> 
> > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> > index 9df1788..2ad5edb 100644
> > --- a/include/hw/pci/pci_bus.h
> > +++ b/include/hw/pci/pci_bus.h
> > @@ -23,6 +23,7 @@ struct PCIBus {
> >      PCIDevice *parent_dev;
> >      MemoryRegion *address_space_mem;
> >      MemoryRegion *address_space_io;
> > +    MemoryRegion master_abort_mem;
> >  
> 
> Looks like this field is left uninitialized for bridge
> devices (they don't seem to call pci_bus_init)?
The bridges have no influence with respect to master_abort_mem
as it handles *all* unassigned addresses for PCI address space.
As stated above, it was tested.

Thanks,
Marcel
 

> 
> >      QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> >      QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> > -- 
> > 1.8.3.1

Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort

[Michael S. Tsirkin]

On Mon, Sep 16, 2013 at 12:11:32PM +0300, Marcel Apfelbaum wrote:
> On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
> > > A MemoryRegion with negative priority was created and
> > > it spans over all the pci address space.
> > > It "intercepts" the accesses to unassigned pci
> > > address space and will follow the pci spec:
> > >  1. returns -1 on read
> > >  2. does nothing on write
> > > 
> > > Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
> > >       of the device that initiated the transaction will be
> > >       implemented in another series
> > > 
> > > Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>

So let's hold on to this patch and see how the full
implementation interacts with it.
Let's apply 1-2 - I'll put it on my tree unless someone objects.

> > > ---
> > > Changes from v4:
> > >  - Addressed Michael S. Tsirkin comments
> > >    - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
> > >  - Fixed: overlap master_abort_mem at offset 0, not at
> > >           bus->address_space_mem.addr
> > > 
> > >  hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
> > >  include/hw/pci/pci_bus.h |  1 +
> > >  2 files changed, 27 insertions(+)
> > > 
> > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > > index ad1c1ca..d8a1b11 100644
> > > --- a/hw/pci/pci.c
> > > +++ b/hw/pci/pci.c
> > > @@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
> > >      return rootbus->qbus.name;
> > >  }
> > >  
> > > +static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
> > > +{
> > > +   return -1ULL;
> > > +}
> > > +
> > > +static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
> > > +                                   unsigned size)
> > > +{
> > > +}
> > > +
> > > +static const MemoryRegionOps master_abort_mem_ops = {
> > > +    .read = master_abort_mem_read,
> > > +    .write = master_abort_mem_write,
> > > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > > +};
> > > +
> > > +#define MASTER_ABORT_MEM_PRIORITY INT_MIN
> > > +
> > >  static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > >                           const char *name,
> > >                           MemoryRegion *address_space_mem,
> > > @@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > >      bus->address_space_mem = address_space_mem;
> > >      bus->address_space_io = address_space_io;
> > >  
> > > +
> > > +    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
> > > +                          &master_abort_mem_ops, bus, "pci-master-abort",
> > > +                          memory_region_size(bus->address_space_mem));
> > > +    memory_region_add_subregion_overlap(bus->address_space_mem,
> > > +                                        0, &bus->master_abort_mem,
> > > +                                        MASTER_ABORT_MEM_PRIORITY);
> > > +
> > >      /* host bridge */
> > >      QLIST_INIT(&bus->child);
> > >  
> > 
> > Does this handle devices behind bridges?
> Yes, tested also for devices behind bridge.

BTW why does this only handle memory?
IO should be exactly identical, shouldn't it?

> > 
> > 
> > > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> > > index 9df1788..2ad5edb 100644
> > > --- a/include/hw/pci/pci_bus.h
> > > +++ b/include/hw/pci/pci_bus.h
> > > @@ -23,6 +23,7 @@ struct PCIBus {
> > >      PCIDevice *parent_dev;
> > >      MemoryRegion *address_space_mem;
> > >      MemoryRegion *address_space_io;
> > > +    MemoryRegion master_abort_mem;
> > >  
> > 
> > Looks like this field is left uninitialized for bridge
> > devices (they don't seem to call pci_bus_init)?
> The bridges have no influence with respect to master_abort_mem
> as it handles *all* unassigned addresses for PCI address space.
> As stated above, it was tested.
> 
> Thanks,
> Marcel
>  
> 
> > 
> > >      QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> > >      QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> > > -- 
> > > 1.8.3.1
> 
> 

Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort

[Marcel Apfelbaum]

On Mon, 2013-09-16 at 12:51 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 16, 2013 at 12:11:32PM +0300, Marcel Apfelbaum wrote:
> > On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
> > > > A MemoryRegion with negative priority was created and
> > > > it spans over all the pci address space.
> > > > It "intercepts" the accesses to unassigned pci
> > > > address space and will follow the pci spec:
> > > >  1. returns -1 on read
> > > >  2. does nothing on write
> > > > 
> > > > Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
> > > >       of the device that initiated the transaction will be
> > > >       implemented in another series
> > > > 
> > > > Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
> 
> So let's hold on to this patch and see how the full
> implementation interacts with it.
> Let's apply 1-2 - I'll put it on my tree unless someone objects.
> 
> > > > ---
> > > > Changes from v4:
> > > >  - Addressed Michael S. Tsirkin comments
> > > >    - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
> > > >  - Fixed: overlap master_abort_mem at offset 0, not at
> > > >           bus->address_space_mem.addr
> > > > 
> > > >  hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
> > > >  include/hw/pci/pci_bus.h |  1 +
> > > >  2 files changed, 27 insertions(+)
> > > > 
> > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > > > index ad1c1ca..d8a1b11 100644
> > > > --- a/hw/pci/pci.c
> > > > +++ b/hw/pci/pci.c
> > > > @@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
> > > >      return rootbus->qbus.name;
> > > >  }
> > > >  
> > > > +static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
> > > > +{
> > > > +   return -1ULL;
> > > > +}
> > > > +
> > > > +static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
> > > > +                                   unsigned size)
> > > > +{
> > > > +}
> > > > +
> > > > +static const MemoryRegionOps master_abort_mem_ops = {
> > > > +    .read = master_abort_mem_read,
> > > > +    .write = master_abort_mem_write,
> > > > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > > > +};
> > > > +
> > > > +#define MASTER_ABORT_MEM_PRIORITY INT_MIN
> > > > +
> > > >  static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > > >                           const char *name,
> > > >                           MemoryRegion *address_space_mem,
> > > > @@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > > >      bus->address_space_mem = address_space_mem;
> > > >      bus->address_space_io = address_space_io;
> > > >  
> > > > +
> > > > +    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
> > > > +                          &master_abort_mem_ops, bus, "pci-master-abort",
> > > > +                          memory_region_size(bus->address_space_mem));
> > > > +    memory_region_add_subregion_overlap(bus->address_space_mem,
> > > > +                                        0, &bus->master_abort_mem,
> > > > +                                        MASTER_ABORT_MEM_PRIORITY);
> > > > +
> > > >      /* host bridge */
> > > >      QLIST_INIT(&bus->child);
> > > >  
> > > 
> > > Does this handle devices behind bridges?
> > Yes, tested also for devices behind bridge.
> 
> BTW why does this only handle memory?
> IO should be exactly identical, shouldn't it?
IO is handled on a higher level by Jan Kiszka patch:
    [Qemu-devel] [PATCH v3 1/2] memory: Provide separate handling of unassigned io ports accesses

Thanks,
Marcel

> 
> > > 
> > > 
> > > > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> > > > index 9df1788..2ad5edb 100644
> > > > --- a/include/hw/pci/pci_bus.h
> > > > +++ b/include/hw/pci/pci_bus.h
> > > > @@ -23,6 +23,7 @@ struct PCIBus {
> > > >      PCIDevice *parent_dev;
> > > >      MemoryRegion *address_space_mem;
> > > >      MemoryRegion *address_space_io;
> > > > +    MemoryRegion master_abort_mem;
> > > >  
> > > 
> > > Looks like this field is left uninitialized for bridge
> > > devices (they don't seem to call pci_bus_init)?
> > The bridges have no influence with respect to master_abort_mem
> > as it handles *all* unassigned addresses for PCI address space.
> > As stated above, it was tested.
> > 
> > Thanks,
> > Marcel
> >  
> > 
> > > 
> > > >      QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> > > >      QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> > > > -- 
> > > > 1.8.3.1
> > 
> > 

Re: [Qemu-devel] [PATCH v5 0/3] pci: partially implement master abort protocol

[Michael S. Tsirkin]

On Mon, Sep 16, 2013 at 11:21:13AM +0300, Marcel Apfelbaum wrote:
> PCI spec requires that a transaction that has not been claimed
> by any PCI bus devices will be terminated by the initiator
> with "master abort". For read transactions -1(FFFFFFFF) is returned and 
> writes are silently dropped.

OK looks good to me, I put this on the pci branch.

> Implementation:
>  - Allowed the MemoryRegion priority to be negative so a subregion will be
>    visible on all the addresses not covered by other container subregions.
>  - Added a memory region with negative priority that extends over all the
>    pci address space. This region catches all the accesses
>    to the unassigned pci addresses.
>  - The MemoryRegion's ops emulates the master abort scenario.
> 
> I am working on implementing the following on top of this series
>  - Implement upstream master abort
>  - Handling of RECEIVED MASTER ABORT BIT in Status register
> 
> Changes from v4:
>  - Addressed Peter Maydell comments
>    - Changed memory patches commit comment
>  - Addressed Michael S. Tsirkin comments
>    - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
> 
> Changes from v3:
>  - Addressed Peter Maydell comments
>    - Removed unnecessary changes to priority of MemoryListener
>    - Ensured that priority is now signed in all related places
>    - Added to memory docs explanation on signed priorities
>  - Addresses Michael S. Tsirkin comments
>    - Changed the name of the new Memory region to master_abort_mem
>    - Made master abort priority INT_MIN instead of -1
>  - Removed handling of RECEIVED MASTER ABORT BIT; it will be taken
>    care in a different series
> 
> Changes from v2:
>  - minor: changed nr of patches in the title
>  - minor: modified series list
> 
> Changes from v1:
>  - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on
>     various Host Bridges
>  - "pci-unassgined-mem" does not have a ".valid.accept" field and
>     implements read write methods
> 
> Marcel Apfelbaum (3):
>   memory: Change MemoryRegion priorities from unsigned to signed
>   docs/memory: Explictly state that MemoryRegion priority is signed
>   hw/pci: partially handle pci master abort
> 
>  docs/memory.txt          |  4 ++++
>  hw/core/sysbus.c         |  4 ++--
>  hw/pci/pci.c             | 27 +++++++++++++++++++++++++++
>  include/exec/memory.h    |  4 ++--
>  include/hw/pci/pci_bus.h |  1 +
>  include/hw/sysbus.h      |  2 +-
>  memory.c                 |  4 ++--
>  7 files changed, 39 insertions(+), 7 deletions(-)
> 
> -- 
> 1.8.3.1