From: Gleb Natapov <gleb@redhat.com>
To: Eduardo Habkost <ehabkost@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Bandan Das" <bsd@redhat.com>,
qemu-devel@nongnu.org, "Igor Mammedov" <imammedo@redhat.com>,
"Andreas Färber" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models
Date: Sun, 22 Sep 2013 09:36:18 +0300 [thread overview]
Message-ID: <20130922063617.GB25202@redhat.com> (raw)
In-Reply-To: <1379704517-19177-1-git-send-email-ehabkost@redhat.com>
On Fri, Sep 20, 2013 at 04:15:17PM -0300, Eduardo Habkost wrote:
> This enables x2apic on the following CPU models: Conroe, Penryn,
> Nehalem, Westmere, Opteron_G[12345].
>
> Normally we try to keep the CPU model definitions as close as the real
> CPUs as possible, but x2apic can be emulated by KVM without host CPU
> support for x2apic, and it improves performance by reducing APIC access
> overhead. x2apic emulation is available on KVM since 2009 (Linux
> 2.6.32-rc1), there's no reason for not enabling x2apic by default when
> running KVM.
>
> About testing: Conroe, Penryn, Nehalem, Westemere and Opteron_G[123]
> have x2apic enabled on RHEL-6 since RHEL-6.0, so the presence of x2apic
> on those CPU models got lots of testing in the last few years. I want to
> eventually enable x2apic on all other CPU models as well, but it will
> require some testing to ensure it won't confuse guests.
>
> This shouldn't affect TCG at all because features not supported by TCG
> are automatically and silently disabled by QEMU when initializing the
> CPU.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Acked-by: Gleb Natapov <gleb@redhat.com>
> ---
> hw/i386/pc_piix.c | 9 +++++++++
> hw/i386/pc_q35.c | 9 +++++++++
> target-i386/cpu.c | 37 +++++++++++++++++++------------------
> 3 files changed, 37 insertions(+), 18 deletions(-)
>
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 907792b..0af00ef 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -240,6 +240,15 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
> {
> has_pci_info = false;
> rom_file_in_ram = false;
> + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> }
>
> static void pc_compat_1_5(QEMUMachineInitArgs *args)
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index ca84e1c..82e7a23 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -224,6 +224,15 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
> {
> has_pci_info = false;
> rom_file_in_ram = false;
> + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> }
>
> static void pc_compat_1_5(QEMUMachineInitArgs *args)
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 9abb73f..23a44c3 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -791,7 +791,7 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> + CPUID_EXT_X2APIC | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
> .features[FEAT_8000_0001_ECX] =
> @@ -813,8 +813,8 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> - CPUID_EXT_SSE3,
> + CPUID_EXT_X2APIC | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> + CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
> .features[FEAT_8000_0001_ECX] =
> @@ -836,8 +836,8 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> - CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> .features[FEAT_8000_0001_ECX] =
> @@ -859,9 +859,9 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> - CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> - CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> + CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC |
> + CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> + CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> .features[FEAT_8000_0001_ECX] =
> @@ -943,7 +943,7 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_SSE3,
> + CPUID_EXT_X2APIC | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
> @@ -968,7 +968,7 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_CX16 | CPUID_EXT_SSE3,
> + CPUID_EXT_X2APIC | CPUID_EXT_CX16 | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
> CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> @@ -996,8 +996,8 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> - CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
> - CPUID_EXT_SSE3,
> + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_CX16 |
> + CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
> CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> @@ -1027,9 +1027,9 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> - CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> - CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> - CPUID_EXT_SSE3,
> + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> @@ -1061,9 +1061,10 @@ static x86_def_t builtin_x86_defs[] = {
> CPUID_DE | CPUID_FP87,
> .features[FEAT_1_ECX] =
> CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
> - CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> - CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
> - CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> + CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC |
> + CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> + CPUID_EXT_FMA | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> + CPUID_EXT_SSE3,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
> CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> --
> 1.8.3.1
--
Gleb.
next prev parent reply other threads:[~2013-09-22 6:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-20 19:15 [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models Eduardo Habkost
2013-09-22 6:36 ` Gleb Natapov [this message]
-- strict thread matches above, loose matches on Subject: below --
2014-01-20 14:36 [Qemu-devel] [PATCH] target-i386: enable " Eduardo Habkost
2014-01-20 16:27 ` Andreas Färber
2014-01-20 16:50 ` Eduardo Habkost
2014-01-20 22:18 ` Andreas Färber
2014-01-20 22:13 ` Andreas Färber
2014-01-21 10:03 ` Paolo Bonzini
2014-01-21 14:06 ` Eduardo Habkost
2014-01-21 15:51 ` Andreas Färber
2014-01-21 16:13 ` Paolo Bonzini
2014-02-03 19:01 ` Eduardo Habkost
2014-02-04 14:12 ` Andreas Färber
2014-02-17 13:58 ` Michael S. Tsirkin
2014-02-17 14:47 ` Eduardo Habkost
2014-02-17 16:17 ` Andreas Färber
2014-02-17 17:27 ` Eduardo Habkost
2014-01-21 16:20 ` Eduardo Habkost
2014-01-21 14:06 ` Eduardo Habkost
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20130922063617.GB25202@redhat.com \
--to=gleb@redhat.com \
--cc=afaerber@suse.de \
--cc=bsd@redhat.com \
--cc=ehabkost@redhat.com \
--cc=imammedo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.