From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: backlight combination mode bit is gen4 only
Date: Tue, 24 Sep 2013 17:41:21 +0300 [thread overview]
Message-ID: <20130924144121.GD4531@intel.com> (raw)
In-Reply-To: <1380030279-9745-1-git-send-email-jani.nikula@intel.com>
On Tue, Sep 24, 2013 at 04:44:39PM +0300, Jani Nikula wrote:
> Not valid for later non-PCH split platforms such as VLV.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
The bit is mbz on VLV, so I guess it should be 0, but better safe than
sorry, and it gets rid of a useless register read.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 3bc89a6..8f025c6 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -329,7 +329,7 @@ static int is_backlight_combination_mode(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (INTEL_INFO(dev)->gen >= 4)
> + if (IS_GEN4(dev))
> return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
>
> if (IS_GEN2(dev))
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-09-24 14:41 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-24 13:44 [PATCH] drm/i915: backlight combination mode bit is gen4 only Jani Nikula
2013-09-24 14:41 ` Ville Syrjälä [this message]
2013-09-24 15:04 ` Daniel Vetter
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