From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: backlight combination mode bit is gen4 only
Date: Tue, 24 Sep 2013 17:04:39 +0200 [thread overview]
Message-ID: <20130924150413.GA12663@phenom.ffwll.local> (raw)
In-Reply-To: <20130924144121.GD4531@intel.com>
On Tue, Sep 24, 2013 at 05:41:21PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 24, 2013 at 04:44:39PM +0300, Jani Nikula wrote:
> > Not valid for later non-PCH split platforms such as VLV.
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> The bit is mbz on VLV, so I guess it should be 0, but better safe than
> sorry, and it gets rid of a useless register read.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-09-24 15:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-24 13:44 [PATCH] drm/i915: backlight combination mode bit is gen4 only Jani Nikula
2013-09-24 14:41 ` Ville Syrjälä
2013-09-24 15:04 ` Daniel Vetter [this message]
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