From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: "Chew, Chiau Ee" <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: Mika Westerberg
<mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
Christian Ruppert
<christian.ruppert-ux6zf3SgZrrQT0dZR+AlfA@public.gmane.org>,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] i2c-designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set.
Date: Fri, 27 Sep 2013 04:22:35 +0200 [thread overview]
Message-ID: <20130927022234.GA3159@katana> (raw)
In-Reply-To: <1380221855-14150-1-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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On Fri, Sep 27, 2013 at 02:57:35AM +0800, Chew, Chiau Ee wrote:
> According to Designware I2C spec, if I2C_DYNAMIC_TAR_UPDATE is set to 1,
> the 10-bit addressing mode is controlled by IC_10BITADDR_MASTER bit of
> IC_TAR register instead of IC_CON register. The IC_10BITADDR_MASTER
> in IC_CON register becomes read-only copy. Since I2C_DYNAMIC_TAR_UPDATE
> value can't be detected from hardware register, so we will always set the
> IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit
> addresing mode is requested by user application.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Applied to for-current, thanks!
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@the-dreams.de>
To: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
Christian Ruppert <christian.ruppert@abilis.com>,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] i2c-designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set.
Date: Fri, 27 Sep 2013 04:22:35 +0200 [thread overview]
Message-ID: <20130927022234.GA3159@katana> (raw)
In-Reply-To: <1380221855-14150-1-git-send-email-chiau.ee.chew@intel.com>
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On Fri, Sep 27, 2013 at 02:57:35AM +0800, Chew, Chiau Ee wrote:
> According to Designware I2C spec, if I2C_DYNAMIC_TAR_UPDATE is set to 1,
> the 10-bit addressing mode is controlled by IC_10BITADDR_MASTER bit of
> IC_TAR register instead of IC_CON register. The IC_10BITADDR_MASTER
> in IC_CON register becomes read-only copy. Since I2C_DYNAMIC_TAR_UPDATE
> value can't be detected from hardware register, so we will always set the
> IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit
> addresing mode is requested by user application.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Applied to for-current, thanks!
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next prev parent reply other threads:[~2013-09-27 2:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-26 18:57 [PATCH] i2c-designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set Chew, Chiau Ee
2013-09-26 18:57 ` Chew, Chiau Ee
[not found] ` <1380221855-14150-1-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2013-09-27 2:22 ` Wolfram Sang [this message]
2013-09-27 2:22 ` Wolfram Sang
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