From: Tony Lindgren <tony@atomide.com>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>,
linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org,
rnayak@ti.com
Subject: Re: [PATCH] ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
Date: Tue, 8 Oct 2013 14:27:18 -0700 [thread overview]
Message-ID: <20131008212718.GS8313@atomide.com> (raw)
In-Reply-To: <5239A98E.3060908@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [130918 06:32]:
> On Wednesday 18 September 2013 07:20 AM, Sricharan R wrote:
> > The real time counter also called master counter, is a free-running
> > counter. It produces the count used by the CPU local timer peripherals
> > in the MPU cluster. The timer counts at a rate of 6.144 MHz.
> >
> > The ratio registers are missing for a sys-clk of 20MHZ which is used
> > by DRA7 socs. So because of this, the counter was getting wrongly
> > programmed for a sys-clk of 38.4Mhz(default). So adding the ratio
> > registers for 20MHZ sys-clk.
> >
> > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > Signed-off-by: Sricharan R <r.sricharan@ti.com>
> > ---
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Applying into omap-for-v3.13/soc thanks.
Tony
WARNING: multiple messages have this Message-ID (diff)
From: tony@atomide.com (Tony Lindgren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
Date: Tue, 8 Oct 2013 14:27:18 -0700 [thread overview]
Message-ID: <20131008212718.GS8313@atomide.com> (raw)
In-Reply-To: <5239A98E.3060908@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [130918 06:32]:
> On Wednesday 18 September 2013 07:20 AM, Sricharan R wrote:
> > The real time counter also called master counter, is a free-running
> > counter. It produces the count used by the CPU local timer peripherals
> > in the MPU cluster. The timer counts at a rate of 6.144 MHz.
> >
> > The ratio registers are missing for a sys-clk of 20MHZ which is used
> > by DRA7 socs. So because of this, the counter was getting wrongly
> > programmed for a sys-clk of 38.4Mhz(default). So adding the ratio
> > registers for 20MHZ sys-clk.
> >
> > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > Signed-off-by: Sricharan R <r.sricharan@ti.com>
> > ---
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Applying into omap-for-v3.13/soc thanks.
Tony
next prev parent reply other threads:[~2013-10-08 21:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-18 11:20 [PATCH] ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency Sricharan R
2013-09-18 11:20 ` Sricharan R
2013-09-18 12:56 ` [PATCH] ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency\ Nishanth Menon
2013-09-18 12:56 ` Nishanth Menon
2013-09-18 13:24 ` [PATCH] ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency Santosh Shilimkar
2013-09-18 13:24 ` Santosh Shilimkar
2013-10-08 21:27 ` Tony Lindgren [this message]
2013-10-08 21:27 ` Tony Lindgren
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