From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] clocksource: Add Allwinner SoCs HS timers driver
Date: Thu, 10 Oct 2013 21:13:11 +0200 [thread overview]
Message-ID: <20131010191311.GL3041@lukather> (raw)
In-Reply-To: <52436EBE.9010002@codeaurora.org>
Hi Stephen,
Just following back on this.
On Wed, Sep 25, 2013 at 04:16:14PM -0700, Stephen Boyd wrote:
> On 09/25/13 07:03, Maxime Ripard wrote:
> > + sun5i_clockevent.cpumask = cpumask_of(0);
>
> Can this timer interrupt any CPU or is it hardwired to CPU0? If the
> interrupt can go to any CPU this should be cpu_possible_mask instead.
I've changed the few other things you spotted, but this one making the
timer unusable.
I think what happens here is that we have the A31 I've tested these
patches on is a quad-core SoC. As such, the device tree has 4 CPUs
declared. However, we don't have any SMP support for it now. So we end
up having 4 cpus set as possible, and only one online (the boot cpu),
which isn't working.
Would using cpu_online_mask work in our case?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Emilio Lopez <emilio@elopez.com.ar>,
linux-kernel@vger.kernel.org, kevin.z.m.zh@gmail.com,
sunny@allwinnertech.com, shuge@allwinnertech.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/5] clocksource: Add Allwinner SoCs HS timers driver
Date: Thu, 10 Oct 2013 21:13:11 +0200 [thread overview]
Message-ID: <20131010191311.GL3041@lukather> (raw)
In-Reply-To: <52436EBE.9010002@codeaurora.org>
[-- Attachment #1: Type: text/plain, Size: 926 bytes --]
Hi Stephen,
Just following back on this.
On Wed, Sep 25, 2013 at 04:16:14PM -0700, Stephen Boyd wrote:
> On 09/25/13 07:03, Maxime Ripard wrote:
> > + sun5i_clockevent.cpumask = cpumask_of(0);
>
> Can this timer interrupt any CPU or is it hardwired to CPU0? If the
> interrupt can go to any CPU this should be cpu_possible_mask instead.
I've changed the few other things you spotted, but this one making the
timer unusable.
I think what happens here is that we have the A31 I've tested these
patches on is a quad-core SoC. As such, the device tree has 4 CPUs
declared. However, we don't have any SMP support for it now. So we end
up having 4 cpus set as possible, and only one online (the boot cpu),
which isn't working.
Would using cpu_online_mask work in our case?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2013-10-10 19:13 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-25 14:03 [PATCH 0/5] Allwinner SoCs High Speed Timer support Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 14:03 ` [PATCH 1/5] clocksource: sun4i: Select CLKSRC_MMIO Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 14:03 ` [PATCH 2/5] clocksource: Add Allwinner SoCs HS timers driver Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 23:16 ` Stephen Boyd
2013-09-25 23:16 ` Stephen Boyd
2013-09-26 12:58 ` Maxime Ripard
2013-09-26 12:58 ` Maxime Ripard
2013-10-10 19:13 ` Maxime Ripard [this message]
2013-10-10 19:13 ` Maxime Ripard
2013-10-10 22:46 ` Stephen Boyd
2013-10-10 22:46 ` Stephen Boyd
2013-10-11 18:33 ` Maxime Ripard
2013-10-11 18:33 ` Maxime Ripard
2013-09-25 23:23 ` Emilio López
2013-09-25 23:23 ` Emilio López
2013-09-26 13:13 ` Maxime Ripard
2013-09-26 13:13 ` Maxime Ripard
2013-09-29 4:34 ` Emilio López
2013-09-29 4:34 ` Emilio López
2013-09-29 18:44 ` Maxime Ripard
2013-09-29 18:44 ` Maxime Ripard
2013-09-25 14:03 ` [PATCH 3/5] ARM: sun5i: a10s: Add support for the High Speed Timers Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 14:03 ` [PATCH 4/5] ARM: sun5i: a13: " Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 14:03 ` [PATCH 5/5] ARM: sun7i: a20: " Maxime Ripard
2013-09-25 14:03 ` Maxime Ripard
2013-09-25 18:13 ` [PATCH 0/5] Allwinner SoCs High Speed Timer support Kevin Hilman
2013-09-25 18:13 ` Kevin Hilman
2013-09-25 18:14 ` Olof Johansson
2013-09-25 18:14 ` Olof Johansson
2013-09-25 19:50 ` Maxime Ripard
2013-09-25 19:50 ` Maxime Ripard
2013-09-26 14:39 ` Thomas Petazzoni
2013-09-26 14:39 ` Thomas Petazzoni
2013-09-27 17:05 ` Maxime Ripard
2013-09-27 17:05 ` Maxime Ripard
2013-09-27 17:55 ` Thomas Petazzoni
2013-09-27 17:55 ` Thomas Petazzoni
2013-09-25 20:21 ` Kevin Hilman
2013-09-25 20:21 ` Kevin Hilman
2013-09-25 22:41 ` Emilio López
2013-09-25 22:41 ` Emilio López
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