* [PATCH 0/2] drm/i915: VLV GT wake FIFO stuff
@ 2013-11-13 23:59 ville.syrjala
2013-11-13 23:59 ` [PATCH 1/2] drm/i915: Report all GTFIFODBG errors ville.syrjala
2013-11-14 0:00 ` [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV ville.syrjala
0 siblings, 2 replies; 10+ messages in thread
From: ville.syrjala @ 2013-11-13 23:59 UTC (permalink / raw)
To: intel-gfx
The registers for monitoring the GT wake FIFO have some extra stuff on
VLV. This series tries to fix the code to handle those extra bits slightly
better.
Just compile tested.
Ville Syrjälä (2):
drm/i915: Report all GTFIFODBG errors
drm/i915: Fix GT wake FIFO free entries for VLV
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
drivers/gpu/drm/i915/intel_uncore.c | 11 +++++------
2 files changed, 11 insertions(+), 8 deletions(-)
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-13 23:59 [PATCH 0/2] drm/i915: VLV GT wake FIFO stuff ville.syrjala @ 2013-11-13 23:59 ` ville.syrjala 2013-11-14 12:54 ` Mika Kuoppala 2013-11-14 0:00 ` [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV ville.syrjala 1 sibling, 1 reply; 10+ messages in thread From: ville.syrjala @ 2013-11-13 23:59 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> On VLV GTFIFODBG has more bits. Just report them all. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 849e595..e8f47de 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4852,7 +4852,10 @@ #define FORCEWAKE_MT_ENABLE (1<<5) #define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_SBDROPERR (1<<6) +#define GT_FIFO_BLOBDROPERR (1<<5) +#define GT_FIFO_SB_READ_ABORTERR (1<<4) +#define GT_FIFO_DROPERR (1<<3) #define GT_FIFO_OVFERR (1<<2) #define GT_FIFO_IAWRERR (1<<1) #define GT_FIFO_IARDERR (1<<0) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 0edabbb..a9849ab 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) u32 gtfifodbg; gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, - "MMIO read or write has been dropped %x\n", gtfifodbg)) - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) + __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); } static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-13 23:59 ` [PATCH 1/2] drm/i915: Report all GTFIFODBG errors ville.syrjala @ 2013-11-14 12:54 ` Mika Kuoppala 2013-11-14 17:09 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Mika Kuoppala @ 2013-11-14 12:54 UTC (permalink / raw) To: ville.syrjala, intel-gfx ville.syrjala@linux.intel.com writes: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > On VLV GTFIFODBG has more bits. Just report them all. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 849e595..e8f47de 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4852,7 +4852,10 @@ > #define FORCEWAKE_MT_ENABLE (1<<5) > > #define GTFIFODBG 0x120000 > -#define GT_FIFO_CPU_ERROR_MASK 7 > +#define GT_FIFO_SBDROPERR (1<<6) > +#define GT_FIFO_BLOBDROPERR (1<<5) > +#define GT_FIFO_SB_READ_ABORTERR (1<<4) > +#define GT_FIFO_DROPERR (1<<3) > #define GT_FIFO_OVFERR (1<<2) > #define GT_FIFO_IAWRERR (1<<1) > #define GT_FIFO_IARDERR (1<<0) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 0edabbb..a9849ab 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > u32 gtfifodbg; > > gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); > - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, > - "MMIO read or write has been dropped %x\n", gtfifodbg)) > - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); > + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) I think you still need mask, there are ro fields != 0 in the same register. -Mika > + __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); > } > > static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-14 12:54 ` Mika Kuoppala @ 2013-11-14 17:09 ` Ville Syrjälä 2013-11-18 15:13 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2013-11-14 17:09 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote: > ville.syrjala@linux.intel.com writes: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > On VLV GTFIFODBG has more bits. Just report them all. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > > drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- > > 2 files changed, 6 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 849e595..e8f47de 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4852,7 +4852,10 @@ > > #define FORCEWAKE_MT_ENABLE (1<<5) > > > > #define GTFIFODBG 0x120000 > > -#define GT_FIFO_CPU_ERROR_MASK 7 > > +#define GT_FIFO_SBDROPERR (1<<6) > > +#define GT_FIFO_BLOBDROPERR (1<<5) > > +#define GT_FIFO_SB_READ_ABORTERR (1<<4) > > +#define GT_FIFO_DROPERR (1<<3) > > #define GT_FIFO_OVFERR (1<<2) > > #define GT_FIFO_IAWRERR (1<<1) > > #define GT_FIFO_IARDERR (1<<0) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index 0edabbb..a9849ab 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > > u32 gtfifodbg; > > > > gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); > > - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, > > - "MMIO read or write has been dropped %x\n", gtfifodbg)) > > - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); > > + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) > > I think you still need mask, there are ro fields != 0 in the same > register. Which bits? VLV has those seven low bits, others just three low bits AFAICS. -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-14 17:09 ` Ville Syrjälä @ 2013-11-18 15:13 ` Ville Syrjälä 2013-11-20 17:14 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2013-11-18 15:13 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Thu, Nov 14, 2013 at 07:09:48PM +0200, Ville Syrjälä wrote: > On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote: > > ville.syrjala@linux.intel.com writes: > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > On VLV GTFIFODBG has more bits. Just report them all. > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > > > drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- > > > 2 files changed, 6 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 849e595..e8f47de 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -4852,7 +4852,10 @@ > > > #define FORCEWAKE_MT_ENABLE (1<<5) > > > > > > #define GTFIFODBG 0x120000 > > > -#define GT_FIFO_CPU_ERROR_MASK 7 > > > +#define GT_FIFO_SBDROPERR (1<<6) > > > +#define GT_FIFO_BLOBDROPERR (1<<5) > > > +#define GT_FIFO_SB_READ_ABORTERR (1<<4) > > > +#define GT_FIFO_DROPERR (1<<3) > > > #define GT_FIFO_OVFERR (1<<2) > > > #define GT_FIFO_IAWRERR (1<<1) > > > #define GT_FIFO_IARDERR (1<<0) > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > index 0edabbb..a9849ab 100644 > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > > > u32 gtfifodbg; > > > > > > gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); > > > - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, > > > - "MMIO read or write has been dropped %x\n", gtfifodbg)) > > > - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); > > > + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) > > > > I think you still need mask, there are ro fields != 0 in the same > > register. > > Which bits? VLV has those seven low bits, others just three low bits > AFAICS. OK, so the problem is that bspec seems to list some bogus junk for these registers. The gunit register HAS is what I used to write these patches. Someone with a VLV on their hands should double check whether real hardware agrees with the gunit register HAS. Any volunteers? -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-18 15:13 ` Ville Syrjälä @ 2013-11-20 17:14 ` Ville Syrjälä 2013-11-27 16:53 ` Jesse Barnes 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2013-11-20 17:14 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Mon, Nov 18, 2013 at 05:13:19PM +0200, Ville Syrjälä wrote: > On Thu, Nov 14, 2013 at 07:09:48PM +0200, Ville Syrjälä wrote: > > On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote: > > > ville.syrjala@linux.intel.com writes: > > > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > > > On VLV GTFIFODBG has more bits. Just report them all. > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > > > > drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- > > > > 2 files changed, 6 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > > index 849e595..e8f47de 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -4852,7 +4852,10 @@ > > > > #define FORCEWAKE_MT_ENABLE (1<<5) > > > > > > > > #define GTFIFODBG 0x120000 > > > > -#define GT_FIFO_CPU_ERROR_MASK 7 > > > > +#define GT_FIFO_SBDROPERR (1<<6) > > > > +#define GT_FIFO_BLOBDROPERR (1<<5) > > > > +#define GT_FIFO_SB_READ_ABORTERR (1<<4) > > > > +#define GT_FIFO_DROPERR (1<<3) > > > > #define GT_FIFO_OVFERR (1<<2) > > > > #define GT_FIFO_IAWRERR (1<<1) > > > > #define GT_FIFO_IARDERR (1<<0) > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > index 0edabbb..a9849ab 100644 > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > > > > u32 gtfifodbg; > > > > > > > > gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); > > > > - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, > > > > - "MMIO read or write has been dropped %x\n", gtfifodbg)) > > > > - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); > > > > + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) > > > > > > I think you still need mask, there are ro fields != 0 in the same > > > register. > > > > Which bits? VLV has those seven low bits, others just three low bits > > AFAICS. > > OK, so the problem is that bspec seems to list some bogus junk for these > registers. The gunit register HAS is what I used to write these patches. > Someone with a VLV on their hands should double check whether real > hardware agrees with the gunit register HAS. Any volunteers? Imre had a look on his VLV the other day, and the register contents seemed to match the Gunit register HAS. So I think these patches should be doing the right thing. -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Report all GTFIFODBG errors 2013-11-20 17:14 ` Ville Syrjälä @ 2013-11-27 16:53 ` Jesse Barnes 0 siblings, 0 replies; 10+ messages in thread From: Jesse Barnes @ 2013-11-27 16:53 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Wed, 20 Nov 2013 19:14:17 +0200 Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Mon, Nov 18, 2013 at 05:13:19PM +0200, Ville Syrjälä wrote: > > On Thu, Nov 14, 2013 at 07:09:48PM +0200, Ville Syrjälä wrote: > > > On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote: > > > > ville.syrjala@linux.intel.com writes: > > > > > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > > > > > On VLV GTFIFODBG has more bits. Just report them all. > > > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > > > > > drivers/gpu/drm/i915/intel_uncore.c | 5 ++--- > > > > > 2 files changed, 6 insertions(+), 4 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > > > index 849e595..e8f47de 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > @@ -4852,7 +4852,10 @@ > > > > > #define FORCEWAKE_MT_ENABLE (1<<5) > > > > > > > > > > #define GTFIFODBG 0x120000 > > > > > -#define GT_FIFO_CPU_ERROR_MASK 7 > > > > > +#define GT_FIFO_SBDROPERR (1<<6) > > > > > +#define GT_FIFO_BLOBDROPERR (1<<5) > > > > > +#define GT_FIFO_SB_READ_ABORTERR (1<<4) > > > > > +#define GT_FIFO_DROPERR (1<<3) > > > > > #define GT_FIFO_OVFERR (1<<2) > > > > > #define GT_FIFO_IAWRERR (1<<1) > > > > > #define GT_FIFO_IARDERR (1<<0) > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > > index 0edabbb..a9849ab 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) > > > > > u32 gtfifodbg; > > > > > > > > > > gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); > > > > > - if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, > > > > > - "MMIO read or write has been dropped %x\n", gtfifodbg)) > > > > > - __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); > > > > > + if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) > > > > > > > > I think you still need mask, there are ro fields != 0 in the same > > > > register. > > > > > > Which bits? VLV has those seven low bits, others just three low bits > > > AFAICS. > > > > OK, so the problem is that bspec seems to list some bogus junk for these > > registers. The gunit register HAS is what I used to write these patches. > > Someone with a VLV on their hands should double check whether real > > hardware agrees with the gunit register HAS. Any volunteers? > > Imre had a look on his VLV the other day, and the register contents seemed > to match the Gunit register HAS. So I think these patches should be doing > the right thing. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV 2013-11-13 23:59 [PATCH 0/2] drm/i915: VLV GT wake FIFO stuff ville.syrjala 2013-11-13 23:59 ` [PATCH 1/2] drm/i915: Report all GTFIFODBG errors ville.syrjala @ 2013-11-14 0:00 ` ville.syrjala 2013-11-27 17:04 ` Jesse Barnes 1 sibling, 1 reply; 10+ messages in thread From: ville.syrjala @ 2013-11-14 0:00 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> On VLV the GTFIFOCTL register has other bits besides the number of free entries in the GT wake FIFO. Apply a mask when we read th register to make sure we don't misinterpret the number of free FIFO entries. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 ++- drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e8f47de..e243105 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4860,7 +4860,8 @@ #define GT_FIFO_IAWRERR (1<<1) #define GT_FIFO_IARDERR (1<<0) -#define GT_FIFO_FREE_ENTRIES 0x120008 +#define GTFIFOCTL 0x120008 +#define GT_FIFO_FREE_ENTRIES_MASK 0x7f #define GT_FIFO_NUM_RESERVED_ENTRIES 20 #define HSW_IDICR 0x9008 diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index a9849ab..71902c4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -148,10 +148,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); + u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); + fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -806,7 +806,7 @@ static int gen6_do_reset(struct drm_device *dev) dev_priv->uncore.funcs.force_wake_put(dev_priv); /* Restore fifo count */ - dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); + dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); return ret; -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV 2013-11-14 0:00 ` [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV ville.syrjala @ 2013-11-27 17:04 ` Jesse Barnes 2013-11-27 17:16 ` Daniel Vetter 0 siblings, 1 reply; 10+ messages in thread From: Jesse Barnes @ 2013-11-27 17:04 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Thu, 14 Nov 2013 02:00:00 +0200 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > On VLV the GTFIFOCTL register has other bits besides the number of free > entries in the GT wake FIFO. Apply a mask when we read th register to > make sure we don't misinterpret the number of free FIFO entries. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e8f47de..e243105 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4860,7 +4860,8 @@ > #define GT_FIFO_IAWRERR (1<<1) > #define GT_FIFO_IARDERR (1<<0) > > -#define GT_FIFO_FREE_ENTRIES 0x120008 > +#define GTFIFOCTL 0x120008 > +#define GT_FIFO_FREE_ENTRIES_MASK 0x7f > #define GT_FIFO_NUM_RESERVED_ENTRIES 20 > > #define HSW_IDICR 0x9008 > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index a9849ab..71902c4 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -148,10 +148,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > > if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { > int loop = 500; > - u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > + u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { > udelay(10); > - fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > + fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > } > if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) > ++ret; > @@ -806,7 +806,7 @@ static int gen6_do_reset(struct drm_device *dev) > dev_priv->uncore.funcs.force_wake_put(dev_priv); > > /* Restore fifo count */ > - dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > + dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > return ret; I don't see this reg on HSW, but it looks like our HSW code uses this routine? Assuming the spec is just broken today... at least I see it for other gens. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV 2013-11-27 17:04 ` Jesse Barnes @ 2013-11-27 17:16 ` Daniel Vetter 0 siblings, 0 replies; 10+ messages in thread From: Daniel Vetter @ 2013-11-27 17:16 UTC (permalink / raw) To: Jesse Barnes; +Cc: intel-gfx On Wed, Nov 27, 2013 at 09:04:38AM -0800, Jesse Barnes wrote: > On Thu, 14 Nov 2013 02:00:00 +0200 > ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > On VLV the GTFIFOCTL register has other bits besides the number of free > > entries in the GT wake FIFO. Apply a mask when we read th register to > > make sure we don't misinterpret the number of free FIFO entries. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > 2 files changed, 5 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index e8f47de..e243105 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4860,7 +4860,8 @@ > > #define GT_FIFO_IAWRERR (1<<1) > > #define GT_FIFO_IARDERR (1<<0) > > > > -#define GT_FIFO_FREE_ENTRIES 0x120008 > > +#define GTFIFOCTL 0x120008 > > +#define GT_FIFO_FREE_ENTRIES_MASK 0x7f > > #define GT_FIFO_NUM_RESERVED_ENTRIES 20 > > > > #define HSW_IDICR 0x9008 > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index a9849ab..71902c4 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -148,10 +148,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > > > > if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { > > int loop = 500; > > - u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > > + u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > > while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { > > udelay(10); > > - fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > > + fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > > } > > if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) > > ++ret; > > @@ -806,7 +806,7 @@ static int gen6_do_reset(struct drm_device *dev) > > dev_priv->uncore.funcs.force_wake_put(dev_priv); > > > > /* Restore fifo count */ > > - dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); > > + dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; > > > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > > return ret; > > I don't see this reg on HSW, but it looks like our HSW code uses this > routine? > > Assuming the spec is just broken today... at least I see it for other > gens. > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Both merged with a little note about this one here. We can back it out again ;-) Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-11-27 17:15 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-11-13 23:59 [PATCH 0/2] drm/i915: VLV GT wake FIFO stuff ville.syrjala 2013-11-13 23:59 ` [PATCH 1/2] drm/i915: Report all GTFIFODBG errors ville.syrjala 2013-11-14 12:54 ` Mika Kuoppala 2013-11-14 17:09 ` Ville Syrjälä 2013-11-18 15:13 ` Ville Syrjälä 2013-11-20 17:14 ` Ville Syrjälä 2013-11-27 16:53 ` Jesse Barnes 2013-11-14 0:00 ` [PATCH 2/2] drm/i915: Fix GT wake FIFO free entries for VLV ville.syrjala 2013-11-27 17:04 ` Jesse Barnes 2013-11-27 17:16 ` Daniel Vetter
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