From: Rodrigo Vivi <rodrigo.vivi@gmail.com>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/10] drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRI
Date: Wed, 20 Nov 2013 14:50:15 -0800 [thread overview]
Message-ID: <20131120225015.GC4234@bratislava.jf.intel.com> (raw)
In-Reply-To: <1383771745-22463-6-git-send-email-ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Wed, Nov 06, 2013 at 11:02:20PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The spec tells us that we need to emit an SRM after the LRI
> to MSG_FBC_REND_STATE.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0719c8b..7a4d3e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -235,6 +235,7 @@
> */
> #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
> #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
> +#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 752f208..4649bf5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
> if (!ring->fbc_dirty)
> return 0;
>
> - ret = intel_ring_begin(ring, 4);
> + ret = intel_ring_begin(ring, 6);
> if (ret)
> return ret;
> - intel_ring_emit(ring, MI_NOOP);
> /* WaFbcNukeOn3DBlt:ivb/hsw */
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit(ring, MSG_FBC_REND_STATE);
> intel_ring_emit(ring, value);
> + intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
> + intel_ring_emit(ring, MSG_FBC_REND_STATE);
> + intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
> intel_ring_advance(ring);
>
> ring->fbc_dirty = false;
> --
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2013-11-20 22:50 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-06 21:02 [PATCH 00/10] drm/i915: FBC fixes v2 ville.syrjala
2013-11-06 21:02 ` [PATCH 01/10] drm/i915: Grab struct_mutex around all FBC updates ville.syrjala
2013-11-20 22:39 ` Rodrigo Vivi
2013-11-21 8:22 ` Daniel Vetter
2013-11-21 10:49 ` Ville Syrjälä
2013-11-21 11:08 ` [PATCH v2 " ville.syrjala
2013-11-06 21:02 ` [PATCH 02/10] drm/i915: Have FBC keep references to the fb ville.syrjala
2013-11-21 11:09 ` [PATCH v2 " ville.syrjala
2013-11-06 21:02 ` [PATCH 03/10] drm/i915: Grab crtc->mutex in intel_fbc_work_fn() ville.syrjala
2013-11-06 21:02 ` [PATCH 04/10] drm/i915: Limit FBC flush to post batch flush ville.syrjala
2013-11-20 22:48 ` Rodrigo Vivi
2013-11-06 21:02 ` [PATCH 05/10] drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRI ville.syrjala
2013-11-20 22:50 ` Rodrigo Vivi [this message]
2013-11-06 21:02 ` [PATCH v3 06/10] drm/i915: Implement LRI based FBC tracking ville.syrjala
2013-11-20 22:55 ` Rodrigo Vivi
2013-11-20 23:17 ` Chris Wilson
2013-11-20 23:46 ` Rodrigo Vivi
2013-11-21 11:14 ` [PATCH v4 " ville.syrjala
2013-11-21 11:49 ` Chris Wilson
2013-11-21 16:33 ` Ville Syrjälä
2013-11-21 16:39 ` Chris Wilson
2013-11-22 4:20 ` Ben Widawsky
2013-11-27 15:22 ` [PATCH v5 " ville.syrjala
2013-11-28 11:29 ` Chris Wilson
2013-11-20 23:53 ` [PATCH v3 " Rodrigo Vivi
2013-11-06 21:02 ` [PATCH v2 07/10] drm/i915: Kill sandybridge_blit_fbc_update() ville.syrjala
2013-11-20 22:56 ` Rodrigo Vivi
2013-11-06 21:02 ` [PATCH v2 08/10] drm/i915: Don't write ILK/IVB_FBC_RT_BASE directly ville.syrjala
2013-11-20 22:57 ` Rodrigo Vivi
2013-11-27 15:24 ` [PATCH v3 08/10] drm/i915: Don't write IVB_FBC_RT_BASE ville.syrjala
2013-11-28 11:30 ` Chris Wilson
2013-11-06 21:02 ` [PATCH 09/10] drm/i915: Set has_fbc=true for all SNB+, except VLV ville.syrjala
2013-11-20 23:00 ` Rodrigo Vivi
2013-11-06 21:02 ` [PATCH 10/10] drm/i915: Use plane_name() in gen7_enable_fbc() ville.syrjala
2013-11-20 23:01 ` Rodrigo Vivi
2013-11-21 8:08 ` Daniel Vetter
2013-11-21 9:57 ` Chris Wilson
2013-11-21 10:55 ` Ville Syrjälä
2013-11-21 9:03 ` [PATCH 00/10] drm/i915: FBC fixes v2 Rodrigo Vivi
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