From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
plagnioj-sclMFOaUSTBWk0Htik3J/w@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2] ARM: at91: sama5d3: reduce TWI internal clock frequency
Date: Fri, 22 Nov 2013 17:25:41 +0100 [thread overview]
Message-ID: <20131122162541.GE7420@katana> (raw)
In-Reply-To: <1385136523-11962-1-git-send-email-ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
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On Fri, Nov 22, 2013 at 05:08:43PM +0100, ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org wrote:
> From: Ludovic Desroches <ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>
> With some devices, transfer hangs during I2C frame transmission. This issue
> disappears when reducing the internal frequency of the TWI IP. Even if it is
> indicated that internal clock max frequency is 66MHz, it seems we have
> oversampling on I2C signals making TWI believe that a transfer in progress
> is done.
>
> This fix has no impact on the I2C bus frequency.
>
> Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> #3.10+
> Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Ludovic Desroches <ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Acked-by: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
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From: wsa@the-dreams.de (Wolfram Sang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] ARM: at91: sama5d3: reduce TWI internal clock frequency
Date: Fri, 22 Nov 2013 17:25:41 +0100 [thread overview]
Message-ID: <20131122162541.GE7420@katana> (raw)
In-Reply-To: <1385136523-11962-1-git-send-email-ludovic.desroches@atmel.com>
On Fri, Nov 22, 2013 at 05:08:43PM +0100, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches@atmel.com>
>
> With some devices, transfer hangs during I2C frame transmission. This issue
> disappears when reducing the internal frequency of the TWI IP. Even if it is
> indicated that internal clock max frequency is 66MHz, it seems we have
> oversampling on I2C signals making TWI believe that a transfer in progress
> is done.
>
> This fix has no impact on the I2C bus frequency.
>
> Cc: <stable@vger.kernel.org> #3.10+
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
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next prev parent reply other threads:[~2013-11-22 16:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-22 16:08 [PATCH v2] ARM: at91: sama5d3: reduce TWI internal clock frequency ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w
2013-11-22 16:08 ` ludovic.desroches at atmel.com
[not found] ` <1385136523-11962-1-git-send-email-ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2013-11-22 16:25 ` Wolfram Sang [this message]
2013-11-22 16:25 ` Wolfram Sang
2013-12-02 8:42 ` Nicolas Ferre
2013-12-02 8:42 ` Nicolas Ferre
[not found] ` <529C47E3.2010508-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2013-12-02 10:56 ` Nicolas Ferre
2013-12-02 10:56 ` Nicolas Ferre
2013-11-22 18:31 ` Jean-Christophe PLAGNIOL-VILLARD
2013-11-22 18:31 ` Jean-Christophe PLAGNIOL-VILLARD
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