Re: [PATCH v6 4/5] MCS Lock: Barrier corrections

["Paul E. McKenney" <paulmck@linux.vnet.ibm.com>]

On Fri, Nov 22, 2013 at 06:11:52PM -0800, Linus Torvalds wrote:
> On Fri, Nov 22, 2013 at 5:36 PM, Paul E. McKenney
> <paulmck@linux.vnet.ibm.com> wrote:
> >
> > So there is your example.  It really can and does happen.
> >
> > Again, easy fix.  Just change powerpc's smp_store_release() from lwsync
> > to smp_mb().  That fixes the problem and doesn't hurt anyone but powerpc.
> >
> > OK?
> 
> Hmm. Ok
> 
> Except now I'm worried it can happen on x86 too because my mental
> model was clearly wrong.
> 
> x86 does have that extra "Memory ordering obeys causality (memory
> ordering respects transitive visibility)." rule, and the example in
> the architecture manual (section 8.2.3.6 "Stores Are Transitively
> Visible") seems to very much about this, but your particular example
> is subtly different, so..

Indeed, my example needs CPU 1's -load- from y to be transitively visible,
so I am nervous about this one as well.

> I will have to ruminate on this.

The rules on the left-hand column of page 5 of the below URL apply to
this example more straightforwardly, but I don't know that Intel and
AMD stand behind them:

	http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf

My guess is that x86 does guarantee this ordering, but at this point I
would have to ask someone from Intel and AMD.

							Thanx, Paul

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