From: Borislav Petkov <bp@alien8.de>
To: Qiaowei Ren <qiaowei.ren@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
Xudong Hao <xudong.hao@intel.com>,
Liu Jinsong <jinsong.liu@intel.com>
Subject: Re: [PATCH 3/3] X86, mpx: Intel MPX xstate feature definition
Date: Fri, 6 Dec 2013 14:46:31 +0100 [thread overview]
Message-ID: <20131206134631.GD6694@pd.tnic> (raw)
In-Reply-To: <1386355976-11732-3-git-send-email-qiaowei.ren@intel.com>
On Sat, Dec 07, 2013 at 02:52:56AM +0800, Qiaowei Ren wrote:
Commit message please.
> Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> arch/x86/include/asm/processor.h | 23 +++++++++++++++++++++++
> arch/x86/include/asm/xsave.h | 6 +++++-
> 2 files changed, 28 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 987c75e..43be6f6 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -370,6 +370,26 @@ struct ymmh_struct {
> u32 ymmh_space[64];
> };
>
> +struct lwp_struct {
> + u64 lwpcb_addr;
> + u32 flags;
> + u32 buf_head_offset;
> + u64 buf_base;
> + u32 buf_size;
> + u32 filters;
> + u64 saved_event_record[4];
> + u32 event_counter[16];
> +};
> +
> +struct bndregs_struct {
> + u64 bndregs[8];
> +} __packed;
> +
> +struct bndcsr_struct {
> + u64 cfg_reg_u;
> + u64 status_reg;
> +} __packed;
> +
> struct xsave_hdr_struct {
> u64 xstate_bv;
> u64 reserved1[2];
> @@ -380,6 +400,9 @@ struct xsave_struct {
> struct i387_fxsave_struct i387;
> struct xsave_hdr_struct xsave_hdr;
> struct ymmh_struct ymmh;
> + struct lwp_struct lwp;
I'm guessing this and the struct lwp_struct above is being added so that
you can have the LWP XSAVE area size? If so, you don't need it: LWP
XSAVE area is 128 bytes at offset 832 according to my manuals so I'd
guess having a u8 lwp_area[128] should be fine.
> + struct bndregs_struct bndregs;
> + struct bndcsr_struct bndcsr;
> /* new processor state extensions will go here */
> } __attribute__ ((packed, aligned (64)));
>
> diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
> index 0415cda..5cd9de3 100644
> --- a/arch/x86/include/asm/xsave.h
> +++ b/arch/x86/include/asm/xsave.h
> @@ -9,6 +9,8 @@
> #define XSTATE_FP 0x1
> #define XSTATE_SSE 0x2
> #define XSTATE_YMM 0x4
> +#define XSTATE_BNDREGS 0x8
> +#define XSTATE_BNDCSR 0x10
>
> #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
>
> @@ -20,10 +22,12 @@
> #define XSAVE_YMM_SIZE 256
> #define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
>
> +#define XSTATE_FLEXIBLE (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
What's the use of that macro if it is used only once?
> +#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
> /*
> * These are the features that the OS can handle currently.
> */
> -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
> +#define XCNTXT_MASK (XSTATE_FLEXIBLE | XSTATE_EAGER)
>
> #ifdef CONFIG_X86_64
> #define REX_PREFIX "0x48, "
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
WARNING: multiple messages have this Message-ID (diff)
From: Borislav Petkov <bp@alien8.de>
To: Qiaowei Ren <qiaowei.ren@intel.com>
Cc: Liu Jinsong <jinsong.liu@intel.com>,
kvm@vger.kernel.org, x86@kernel.org,
Xudong Hao <xudong.hao@intel.com>,
linux-kernel@vger.kernel.org, qemu-devel@nongnu.org,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [Qemu-devel] [PATCH 3/3] X86, mpx: Intel MPX xstate feature definition
Date: Fri, 6 Dec 2013 14:46:31 +0100 [thread overview]
Message-ID: <20131206134631.GD6694@pd.tnic> (raw)
In-Reply-To: <1386355976-11732-3-git-send-email-qiaowei.ren@intel.com>
On Sat, Dec 07, 2013 at 02:52:56AM +0800, Qiaowei Ren wrote:
Commit message please.
> Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> arch/x86/include/asm/processor.h | 23 +++++++++++++++++++++++
> arch/x86/include/asm/xsave.h | 6 +++++-
> 2 files changed, 28 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 987c75e..43be6f6 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -370,6 +370,26 @@ struct ymmh_struct {
> u32 ymmh_space[64];
> };
>
> +struct lwp_struct {
> + u64 lwpcb_addr;
> + u32 flags;
> + u32 buf_head_offset;
> + u64 buf_base;
> + u32 buf_size;
> + u32 filters;
> + u64 saved_event_record[4];
> + u32 event_counter[16];
> +};
> +
> +struct bndregs_struct {
> + u64 bndregs[8];
> +} __packed;
> +
> +struct bndcsr_struct {
> + u64 cfg_reg_u;
> + u64 status_reg;
> +} __packed;
> +
> struct xsave_hdr_struct {
> u64 xstate_bv;
> u64 reserved1[2];
> @@ -380,6 +400,9 @@ struct xsave_struct {
> struct i387_fxsave_struct i387;
> struct xsave_hdr_struct xsave_hdr;
> struct ymmh_struct ymmh;
> + struct lwp_struct lwp;
I'm guessing this and the struct lwp_struct above is being added so that
you can have the LWP XSAVE area size? If so, you don't need it: LWP
XSAVE area is 128 bytes at offset 832 according to my manuals so I'd
guess having a u8 lwp_area[128] should be fine.
> + struct bndregs_struct bndregs;
> + struct bndcsr_struct bndcsr;
> /* new processor state extensions will go here */
> } __attribute__ ((packed, aligned (64)));
>
> diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
> index 0415cda..5cd9de3 100644
> --- a/arch/x86/include/asm/xsave.h
> +++ b/arch/x86/include/asm/xsave.h
> @@ -9,6 +9,8 @@
> #define XSTATE_FP 0x1
> #define XSTATE_SSE 0x2
> #define XSTATE_YMM 0x4
> +#define XSTATE_BNDREGS 0x8
> +#define XSTATE_BNDCSR 0x10
>
> #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
>
> @@ -20,10 +22,12 @@
> #define XSAVE_YMM_SIZE 256
> #define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
>
> +#define XSTATE_FLEXIBLE (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
What's the use of that macro if it is used only once?
> +#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
> /*
> * These are the features that the OS can handle currently.
> */
> -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
> +#define XCNTXT_MASK (XSTATE_FLEXIBLE | XSTATE_EAGER)
>
> #ifdef CONFIG_X86_64
> #define REX_PREFIX "0x48, "
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
next prev parent reply other threads:[~2013-12-06 13:46 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-06 18:52 [PATCH 1/3] x86, mpx: add documentation on Intel MPX Qiaowei Ren
2013-12-06 18:52 ` [Qemu-devel] " Qiaowei Ren
2013-12-06 13:26 ` Borislav Petkov
2013-12-06 13:26 ` [Qemu-devel] " Borislav Petkov
2013-12-06 15:55 ` Ren, Qiaowei
2013-12-06 15:55 ` [Qemu-devel] " Ren, Qiaowei
2013-12-06 15:55 ` Ren, Qiaowei
2013-12-06 16:06 ` Borislav Petkov
2013-12-06 16:06 ` [Qemu-devel] " Borislav Petkov
2013-12-06 16:11 ` Ren, Qiaowei
2013-12-06 16:11 ` [Qemu-devel] " Ren, Qiaowei
2013-12-06 16:11 ` Ren, Qiaowei
2013-12-06 18:52 ` [PATCH 2/3] X86, mpx: Intel MPX definition Qiaowei Ren
2013-12-06 18:52 ` [Qemu-devel] " Qiaowei Ren
2013-12-06 13:33 ` Borislav Petkov
2013-12-06 13:33 ` [Qemu-devel] " Borislav Petkov
2013-12-06 15:58 ` H. Peter Anvin
2013-12-06 15:58 ` [Qemu-devel] " H. Peter Anvin
2013-12-06 18:52 ` [PATCH 3/3] X86, mpx: Intel MPX xstate feature definition Qiaowei Ren
2013-12-06 18:52 ` [Qemu-devel] " Qiaowei Ren
2013-12-06 13:46 ` Borislav Petkov [this message]
2013-12-06 13:46 ` Borislav Petkov
2013-12-06 16:08 ` Ren, Qiaowei
2013-12-06 16:08 ` [Qemu-devel] " Ren, Qiaowei
2013-12-06 16:08 ` Ren, Qiaowei
2013-12-06 17:23 ` H. Peter Anvin
2013-12-06 17:23 ` [Qemu-devel] " H. Peter Anvin
2013-12-06 18:55 ` Borislav Petkov
2013-12-06 18:55 ` [Qemu-devel] " Borislav Petkov
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