* [PATCH] arm: mm: add memory type for inner-writeback @ 2013-12-27 4:58 ` Mark Zhang 0 siblings, 0 replies; 6+ messages in thread From: Mark Zhang @ 2013-12-27 4:58 UTC (permalink / raw) To: linux-arm-kernel From: Colin Cross <ccross@android.com> For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Signed-off-by: Gary King <gking@nvidia.com> --- arch/arm/include/asm/pgtable-2level.h | 1 + arch/arm/include/asm/pgtable.h | 3 +++ arch/arm/mm/proc-macros.S | 2 +- arch/arm/mm/proc-v7-2level.S | 4 ++-- arch/arm/mm/proc-xsc3.S | 2 +- arch/arm/mm/proc-xscale.S | 2 +- 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index dfff709fda3c..528b397b6c91 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -141,6 +141,7 @@ #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#define L_PTE_MT_INNER_WB (_AT(pteval_t, 0x05) << 2) /* 0101 (armv6, armv7) */ #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 7d59b524f2af..2b0601a9a18e 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -134,6 +134,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN) #endif +#define pgprot_inner_writeback(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB) + #endif /* __ASSEMBLY__ */ /* diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e3c48a3fe063..fa829840ee16 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -127,7 +127,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index bdd3be4be77a..059a9d7242c2 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ -.equ PRRR, 0xff0a81a8 -.equ NMRR, 0x40e040e0 +.equ PRRR, 0xff0a89a8 +.equ NMRR, 0x40e044e0 /* * Macro for setting up the TTBRx and TTBCR registers. diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index dc1645890042..9c374495e778 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -381,7 +381,7 @@ cpu_xsc3_mt_table: .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB (not present?) .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) .long 0x00 @ unused diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index d19b1cfcad91..2ac1b88e02ac 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -491,7 +491,7 @@ cpu_xscale_mt_table: .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] arm: mm: add memory type for inner-writeback @ 2013-12-27 4:58 ` Mark Zhang 0 siblings, 0 replies; 6+ messages in thread From: Mark Zhang @ 2013-12-27 4:58 UTC (permalink / raw) To: linux, steve.capper, nico, ccross, catalin.marinas, will.deacon, lauraa, akpm, christoffer.dall, viro, gregory.clement, ben-linux, paul.gortmaker Cc: linux-arm-kernel, linux-kernel, Gary King From: Colin Cross <ccross@android.com> For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Signed-off-by: Gary King <gking@nvidia.com> --- arch/arm/include/asm/pgtable-2level.h | 1 + arch/arm/include/asm/pgtable.h | 3 +++ arch/arm/mm/proc-macros.S | 2 +- arch/arm/mm/proc-v7-2level.S | 4 ++-- arch/arm/mm/proc-xsc3.S | 2 +- arch/arm/mm/proc-xscale.S | 2 +- 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index dfff709fda3c..528b397b6c91 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -141,6 +141,7 @@ #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#define L_PTE_MT_INNER_WB (_AT(pteval_t, 0x05) << 2) /* 0101 (armv6, armv7) */ #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 7d59b524f2af..2b0601a9a18e 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -134,6 +134,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN) #endif +#define pgprot_inner_writeback(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB) + #endif /* __ASSEMBLY__ */ /* diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e3c48a3fe063..fa829840ee16 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -127,7 +127,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index bdd3be4be77a..059a9d7242c2 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ -.equ PRRR, 0xff0a81a8 -.equ NMRR, 0x40e040e0 +.equ PRRR, 0xff0a89a8 +.equ NMRR, 0x40e044e0 /* * Macro for setting up the TTBRx and TTBCR registers. diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index dc1645890042..9c374495e778 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -381,7 +381,7 @@ cpu_xsc3_mt_table: .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB (not present?) .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) .long 0x00 @ unused diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index d19b1cfcad91..2ac1b88e02ac 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -491,7 +491,7 @@ cpu_xscale_mt_table: .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] arm: mm: add memory type for inner-writeback 2013-12-27 4:58 ` Mark Zhang @ 2014-01-07 15:09 ` Catalin Marinas -1 siblings, 0 replies; 6+ messages in thread From: Catalin Marinas @ 2014-01-07 15:09 UTC (permalink / raw) To: linux-arm-kernel On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote: > From: Colin Cross <ccross@android.com> > > For streaming-style operations (e.g., software rendering of graphics > surfaces shared with non-coherent DMA devices), the cost of performing > L2 cache maintenance can exceed the benefit of having the larger cache > (this is particularly true for OUTER_CACHE configurations like the ARM > PL2x0). > > This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) > in the tex remapping tables as an inner-writeback-write-allocate, outer > non-cacheable memory type, so that this mapping will be available to > clients which will benefit from the reduced L2 maintenance. > > Signed-off-by: Gary King <gking@nvidia.com> Is Colin signing off this patch as well? > --- a/arch/arm/mm/proc-v7-2level.S > +++ b/arch/arm/mm/proc-v7-2level.S > @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) > * NS1 = PRRR[19] = 1 - normal shareable property > * NOS = PRRR[24+n] = 1 - not outer shareable > */ > -.equ PRRR, 0xff0a81a8 > -.equ NMRR, 0x40e040e0 > +.equ PRRR, 0xff0a89a8 > +.equ NMRR, 0x40e044e0 It should be done for the *-3level files. -- Catalin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm: mm: add memory type for inner-writeback @ 2014-01-07 15:09 ` Catalin Marinas 0 siblings, 0 replies; 6+ messages in thread From: Catalin Marinas @ 2014-01-07 15:09 UTC (permalink / raw) To: Mark Zhang Cc: linux@arm.linux.org.uk, steve.capper@linaro.org, nico@linaro.org, ccross@android.com, Will Deacon, lauraa@codeaurora.org, akpm@linux-foundation.org, christoffer.dall@linaro.org, viro@zeniv.linux.org.uk, gregory.clement@free-electrons.com, ben-linux@fluff.org, paul.gortmaker@windriver.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Gary King On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote: > From: Colin Cross <ccross@android.com> > > For streaming-style operations (e.g., software rendering of graphics > surfaces shared with non-coherent DMA devices), the cost of performing > L2 cache maintenance can exceed the benefit of having the larger cache > (this is particularly true for OUTER_CACHE configurations like the ARM > PL2x0). > > This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) > in the tex remapping tables as an inner-writeback-write-allocate, outer > non-cacheable memory type, so that this mapping will be available to > clients which will benefit from the reduced L2 maintenance. > > Signed-off-by: Gary King <gking@nvidia.com> Is Colin signing off this patch as well? > --- a/arch/arm/mm/proc-v7-2level.S > +++ b/arch/arm/mm/proc-v7-2level.S > @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) > * NS1 = PRRR[19] = 1 - normal shareable property > * NOS = PRRR[24+n] = 1 - not outer shareable > */ > -.equ PRRR, 0xff0a81a8 > -.equ NMRR, 0x40e040e0 > +.equ PRRR, 0xff0a89a8 > +.equ NMRR, 0x40e044e0 It should be done for the *-3level files. -- Catalin ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] arm: mm: add memory type for inner-writeback 2014-01-07 15:09 ` Catalin Marinas @ 2014-01-07 21:37 ` Colin Cross -1 siblings, 0 replies; 6+ messages in thread From: Colin Cross @ 2014-01-07 21:37 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jan 7, 2014 at 7:09 AM, Catalin Marinas <catalin.marinas@arm.com> wrote: > On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote: >> From: Colin Cross <ccross@android.com> >> >> For streaming-style operations (e.g., software rendering of graphics >> surfaces shared with non-coherent DMA devices), the cost of performing >> L2 cache maintenance can exceed the benefit of having the larger cache >> (this is particularly true for OUTER_CACHE configurations like the ARM >> PL2x0). >> >> This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) >> in the tex remapping tables as an inner-writeback-write-allocate, outer >> non-cacheable memory type, so that this mapping will be available to >> clients which will benefit from the reduced L2 maintenance. >> >> Signed-off-by: Gary King <gking@nvidia.com> > > Is Colin signing off this patch as well? > >> --- a/arch/arm/mm/proc-v7-2level.S >> +++ b/arch/arm/mm/proc-v7-2level.S >> @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) >> * NS1 = PRRR[19] = 1 - normal shareable property >> * NOS = PRRR[24+n] = 1 - not outer shareable >> */ >> -.equ PRRR, 0xff0a81a8 >> -.equ NMRR, 0x40e040e0 >> +.equ PRRR, 0xff0a89a8 >> +.equ NMRR, 0x40e044e0 > > It should be done for the *-3level files. > > -- > Catalin I shouldn't have authorship on that patch at all. The original is at https://android.googlesource.com/kernel/tegra/+/fb382752691d74a849996daf77be961ca2cdae97 and I must have screwed up the authorship when fixing conflicts when cherry-picking it to the android-tegra-moto-2.6.39 branch. Please change the author back to "Gary King <gking@nvidia.com>". ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm: mm: add memory type for inner-writeback @ 2014-01-07 21:37 ` Colin Cross 0 siblings, 0 replies; 6+ messages in thread From: Colin Cross @ 2014-01-07 21:37 UTC (permalink / raw) To: Catalin Marinas Cc: Mark Zhang, linux@arm.linux.org.uk, steve.capper@linaro.org, nico@linaro.org, Will Deacon, lauraa@codeaurora.org, akpm@linux-foundation.org, christoffer.dall@linaro.org, viro@zeniv.linux.org.uk, gregory.clement@free-electrons.com, ben-linux@fluff.org, paul.gortmaker@windriver.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Gary King On Tue, Jan 7, 2014 at 7:09 AM, Catalin Marinas <catalin.marinas@arm.com> wrote: > On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote: >> From: Colin Cross <ccross@android.com> >> >> For streaming-style operations (e.g., software rendering of graphics >> surfaces shared with non-coherent DMA devices), the cost of performing >> L2 cache maintenance can exceed the benefit of having the larger cache >> (this is particularly true for OUTER_CACHE configurations like the ARM >> PL2x0). >> >> This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) >> in the tex remapping tables as an inner-writeback-write-allocate, outer >> non-cacheable memory type, so that this mapping will be available to >> clients which will benefit from the reduced L2 maintenance. >> >> Signed-off-by: Gary King <gking@nvidia.com> > > Is Colin signing off this patch as well? > >> --- a/arch/arm/mm/proc-v7-2level.S >> +++ b/arch/arm/mm/proc-v7-2level.S >> @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext) >> * NS1 = PRRR[19] = 1 - normal shareable property >> * NOS = PRRR[24+n] = 1 - not outer shareable >> */ >> -.equ PRRR, 0xff0a81a8 >> -.equ NMRR, 0x40e040e0 >> +.equ PRRR, 0xff0a89a8 >> +.equ NMRR, 0x40e044e0 > > It should be done for the *-3level files. > > -- > Catalin I shouldn't have authorship on that patch at all. The original is at https://android.googlesource.com/kernel/tegra/+/fb382752691d74a849996daf77be961ca2cdae97 and I must have screwed up the authorship when fixing conflicts when cherry-picking it to the android-tegra-moto-2.6.39 branch. Please change the author back to "Gary King <gking@nvidia.com>". ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-01-07 21:38 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-12-27 4:58 [PATCH] arm: mm: add memory type for inner-writeback Mark Zhang 2013-12-27 4:58 ` Mark Zhang 2014-01-07 15:09 ` Catalin Marinas 2014-01-07 15:09 ` Catalin Marinas 2014-01-07 21:37 ` Colin Cross 2014-01-07 21:37 ` Colin Cross
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