From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
To: Tanmay Inamdar <tinamdar@apm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Grant Likely <grant.likely@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Rob Landley <rob@landley.net>,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-pci@vger.kernel.org, patches <patches@apm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jon Masters <jcm@redhat.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH 2/3] arm64: dts: APM X-Gene PCIe device tree nodes
Date: Tue, 7 Jan 2014 10:27:34 -0700 [thread overview]
Message-ID: <20140107172734.GC4227@obsidianresearch.com> (raw)
In-Reply-To: <CACoXjcnykxdjekfmz6B3Ovk-+naCCOCWFZ3t=ZaMWAEPyVs_eQ@mail.gmail.com>
On Mon, Jan 06, 2014 at 06:56:21PM -0800, Tanmay Inamdar wrote:
> > There is some kind of an addressing problem because you've done this:
> >
> > +static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> > + dev->resource[i].start = dev->resource[i].end = 0;
> > + dev->resource[i].flags = 0;
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_BRIDGE_DEVICEID,
> > + xgene_pcie_fixup_bridge);
> >
> > Which is usually a sign that something is wonky with how the HW is
> > being fit into the PCI core.
>
> We map the whole DDR range (eg 256 GB) into host's BAR. The Linux PCI
> resource management tries to fit the host's memory into the ranges
> provided (eg 0xe000000000).
> Please let me know if there is any use case to do this mapping.
If you need to set the bridge's BAR like this, then the bridge is not
non-conforming.. Bridge BAR's should be 0 size unless the bridge
itself has registers.
Do any registers in this config space work properly? Does the
secondary status reflect the physical link status properly?
If it is *really* broken you might just consider hiding it from the
Linux core.
> >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> >> <TAbort- <MAbort- >SERR- <PERR- INTx-
> >> Latency: 0, Cache Line Size: 64 bytes
> >> Region 0: Memory at <ignored> (64-bit, prefetchable)
> >> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> >> I/O behind bridge: 0000f000-00000fff
> >> Memory behind bridge: 00c00000-00cfffff
> >
> > [..]
> >
> >> 01:00.0 Class 0200: Device 15b3:1003
> >> Region 0: Memory at e000c00000 (64-bit, non-prefetchable) [size=1M]
> >> Region 2: Memory at e000000000 (64-bit, prefetchable)
> >> [size=8M]
> >
> > Something funky is going on here too, the 64 bit address e000000000
> > should be reflected in the 'memory behind bridge' above, not
> > truncated.
>
> That's the Mellanox device that is plugged into the system. The
> device's memory gets mapped at '0xe0xxxxxxxx'
Right, but the bridge setup above has:
> >> Memory behind bridge: 00c00000-00cfffff
Which is wrong, it doesn't include the range '0xe0xxxxxxxx'
Jason
WARNING: multiple messages have this Message-ID (diff)
From: jgunthorpe@obsidianresearch.com (Jason Gunthorpe)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 2/3] arm64: dts: APM X-Gene PCIe device tree nodes
Date: Tue, 7 Jan 2014 10:27:34 -0700 [thread overview]
Message-ID: <20140107172734.GC4227@obsidianresearch.com> (raw)
In-Reply-To: <CACoXjcnykxdjekfmz6B3Ovk-+naCCOCWFZ3t=ZaMWAEPyVs_eQ@mail.gmail.com>
On Mon, Jan 06, 2014 at 06:56:21PM -0800, Tanmay Inamdar wrote:
> > There is some kind of an addressing problem because you've done this:
> >
> > +static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> > + dev->resource[i].start = dev->resource[i].end = 0;
> > + dev->resource[i].flags = 0;
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_BRIDGE_DEVICEID,
> > + xgene_pcie_fixup_bridge);
> >
> > Which is usually a sign that something is wonky with how the HW is
> > being fit into the PCI core.
>
> We map the whole DDR range (eg 256 GB) into host's BAR. The Linux PCI
> resource management tries to fit the host's memory into the ranges
> provided (eg 0xe000000000).
> Please let me know if there is any use case to do this mapping.
If you need to set the bridge's BAR like this, then the bridge is not
non-conforming.. Bridge BAR's should be 0 size unless the bridge
itself has registers.
Do any registers in this config space work properly? Does the
secondary status reflect the physical link status properly?
If it is *really* broken you might just consider hiding it from the
Linux core.
> >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> >> <TAbort- <MAbort- >SERR- <PERR- INTx-
> >> Latency: 0, Cache Line Size: 64 bytes
> >> Region 0: Memory at <ignored> (64-bit, prefetchable)
> >> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> >> I/O behind bridge: 0000f000-00000fff
> >> Memory behind bridge: 00c00000-00cfffff
> >
> > [..]
> >
> >> 01:00.0 Class 0200: Device 15b3:1003
> >> Region 0: Memory at e000c00000 (64-bit, non-prefetchable) [size=1M]
> >> Region 2: Memory at e000000000 (64-bit, prefetchable)
> >> [size=8M]
> >
> > Something funky is going on here too, the 64 bit address e000000000
> > should be reflected in the 'memory behind bridge' above, not
> > truncated.
>
> That's the Mellanox device that is plugged into the system. The
> device's memory gets mapped at '0xe0xxxxxxxx'
Right, but the bridge setup above has:
> >> Memory behind bridge: 00c00000-00cfffff
Which is wrong, it doesn't include the range '0xe0xxxxxxxx'
Jason
next prev parent reply other threads:[~2014-01-07 17:27 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-23 8:02 [RFC PATCH 0/3] APM X-Gene PCIe driver Tanmay Inamdar
2013-12-23 8:02 ` Tanmay Inamdar
2013-12-23 8:02 ` [RFC PATCH 1/3] pci: APM X-Gene PCIe controller driver Tanmay Inamdar
2013-12-23 8:02 ` Tanmay Inamdar
2014-01-02 21:08 ` Bjorn Helgaas
2014-01-02 21:08 ` Bjorn Helgaas
2014-01-03 12:07 ` Arnd Bergmann
2014-01-03 12:07 ` Arnd Bergmann
2014-01-07 2:41 ` Tanmay Inamdar
2014-01-07 2:41 ` Tanmay Inamdar
2014-01-07 9:27 ` Arnd Bergmann
2014-01-07 9:27 ` Arnd Bergmann
2014-01-10 1:20 ` Tanmay Inamdar
2014-01-10 1:20 ` Tanmay Inamdar
2014-01-06 1:47 ` Jingoo Han
2014-01-06 1:47 ` Jingoo Han
2014-01-07 2:45 ` Tanmay Inamdar
2014-01-07 2:45 ` Tanmay Inamdar
2014-01-07 3:31 ` Jingoo Han
2014-01-07 3:31 ` Jingoo Han
2013-12-23 8:02 ` [RFC PATCH 2/3] arm64: dts: APM X-Gene PCIe device tree nodes Tanmay Inamdar
2013-12-23 8:02 ` Tanmay Inamdar
2013-12-23 17:46 ` Jason Gunthorpe
2013-12-23 17:46 ` Jason Gunthorpe
2014-01-02 21:56 ` Tanmay Inamdar
2014-01-02 21:56 ` Tanmay Inamdar
2014-01-03 0:52 ` Jason Gunthorpe
2014-01-03 0:52 ` Jason Gunthorpe
2014-01-07 2:56 ` Tanmay Inamdar
2014-01-07 2:56 ` Tanmay Inamdar
2014-01-07 17:27 ` Jason Gunthorpe [this message]
2014-01-07 17:27 ` Jason Gunthorpe
2014-01-10 1:30 ` Tanmay Inamdar
2014-01-10 1:30 ` Tanmay Inamdar
2013-12-23 8:02 ` [RFC PATCH 3/3] dt-bindings: pci: xgene pcie device tree bindings Tanmay Inamdar
2013-12-23 8:02 ` Tanmay Inamdar
2014-01-03 9:49 ` Arnd Bergmann
2014-01-03 9:49 ` Arnd Bergmann
2014-01-03 9:49 ` Arnd Bergmann
2014-01-07 3:04 ` Tanmay Inamdar
2014-01-07 3:04 ` Tanmay Inamdar
2014-01-07 15:35 ` Arnd Bergmann
2014-01-07 15:35 ` Arnd Bergmann
2014-01-07 15:44 ` Arnd Bergmann
2014-01-07 15:44 ` Arnd Bergmann
2014-01-07 18:31 ` Jason Gunthorpe
2014-01-07 18:31 ` Jason Gunthorpe
2014-01-10 1:32 ` Tanmay Inamdar
2014-01-10 1:32 ` Tanmay Inamdar
2014-01-11 0:12 ` Tanmay Inamdar
2014-01-11 0:12 ` Tanmay Inamdar
2014-01-11 13:06 ` Arnd Bergmann
2014-01-11 13:06 ` Arnd Bergmann
2013-12-23 8:56 ` [RFC PATCH 0/3] APM X-Gene PCIe driver Tanmay Inamdar
2013-12-23 8:56 ` Tanmay Inamdar
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