From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation
Date: Wed, 8 Jan 2014 12:29:44 +0100 [thread overview]
Message-ID: <201401081229.45029.arnd@arndb.de> (raw)
In-Reply-To: <1389030097-10822-4-git-send-email-carlo.caione@gmail.com>
On Monday 06 January 2014, Carlo Caione wrote:
> +Allwinner Sunxi NMI Controller
> +==============================
> +
> +Required properties:
> +
> +- compatible : should be "allwinner,sun7i-sc-nmi"
> +- reg : Specifies base physical address and size of the registers.
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 2.
I think you should list what the two cells are so users know what to
put in the irq specifier.
> +sc-nmi-intc at 01c00030 {
> + compatible = "allwinner,sun7i-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01c00030 0x0c>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 0 1>;
> +};
Is <0 0 1> the correct representation of the NMI? This question has recently
come up on IRC and I didn't know the answer at the time.
Arnd
next prev parent reply other threads:[~2014-01-08 11:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-06 17:41 [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
2014-01-06 17:41 ` [PATCH v2 1/3] ARM: sun7i: irqchip: Add irqchip driver for NMI controller Carlo Caione
2014-01-06 17:41 ` [PATCH v2 2/3] ARM: sun7i: dts: Add NMI irqchip support Carlo Caione
2014-01-06 17:41 ` [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation Carlo Caione
2014-01-08 11:29 ` Arnd Bergmann [this message]
2014-01-08 11:49 ` Carlo Caione
2014-01-08 13:03 ` Hans de Goede
2014-01-09 14:00 ` Carlo Caione
2014-01-08 13:09 ` Arnd Bergmann
2014-01-09 13:59 ` [linux-sunxi] " Carlo Caione
2014-01-09 14:37 ` Arnd Bergmann
2014-01-08 10:41 ` [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
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