From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [linux-sunxi] Re: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation
Date: Thu, 9 Jan 2014 15:37:21 +0100 [thread overview]
Message-ID: <201401091537.21584.arnd@arndb.de> (raw)
In-Reply-To: <CAOQ7t2YYr_gphkXnp1OVsR_sHoOdEhVzDMETjJ2FsDz=Pvh7xQ@mail.gmail.com>
On Thursday 09 January 2014, Carlo Caione wrote:
> In Allwinner A20/A31 SoCs NMI controller is an independent module
> external and in cascade with the GIC. It catches the NMI pin's state
> and generates irq to GIC.
> (therefore NMI is not really not Non-maskable but it is a normal interrupt).
> Here is an ascii-plot of the system (thanks to Maxime and the
> Allwinner engineers for this)
>
> +---------+ +-----------+
> | +------------+ FIQ |
> | GIC | | |
> | +------------+ INT CPU |
> +--+---+--+ | |
> | | | |
> | +------+ | |
> | | | |
> +-----+ +--+--+ +---+---+ | |
> | AXP +-+-+ NMI + | ALARM | | |
> +-----+ | +-----+ +---+---+ +-----------+
> | |
> +---------------+
Ah, cool. That certianly makes sense now. Thanks for the explanation.
Arnd
next prev parent reply other threads:[~2014-01-09 14:37 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-06 17:41 [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
2014-01-06 17:41 ` [PATCH v2 1/3] ARM: sun7i: irqchip: Add irqchip driver for NMI controller Carlo Caione
2014-01-06 17:41 ` [PATCH v2 2/3] ARM: sun7i: dts: Add NMI irqchip support Carlo Caione
2014-01-06 17:41 ` [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation Carlo Caione
2014-01-08 11:29 ` Arnd Bergmann
2014-01-08 11:49 ` Carlo Caione
2014-01-08 13:03 ` Hans de Goede
2014-01-09 14:00 ` Carlo Caione
2014-01-08 13:09 ` Arnd Bergmann
2014-01-09 13:59 ` [linux-sunxi] " Carlo Caione
2014-01-09 14:37 ` Arnd Bergmann [this message]
2014-01-08 10:41 ` [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
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