From: Arnd Bergmann <arnd@arndb.de>
To: Dinh Nguyen <dinguyen@altera.com>
Cc: devicetree@vger.kernel.org, dinh.linux@gmail.com,
heiko@sntech.de, bzhao@marvell.com,
Seungwon Jeon <tgih.jun@samsung.com>,
linux-mmc@vger.kernel.org, dianders@chromium.org,
jh80.chung@samsung.com, alim.akhtar@samsung.com,
zhangfei.gao@linaro.org, mturquette@linaro.org, cjb@laptop.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"
Date: Fri, 10 Jan 2014 20:00:25 +0100 [thread overview]
Message-ID: <201401102000.25484.arnd@arndb.de> (raw)
In-Reply-To: <1389369111.13556.29.camel@linux-builds1>
On Friday 10 January 2014, Dinh Nguyen wrote:
> > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > > index f936476..e776512 100644
> > > --- a/arch/arm/boot/dts/socfpga.dtsi
> > > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > > @@ -413,6 +413,7 @@
> > > compatible = "altr,socfpga-gate-clk";
> > > clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > > <&per_nand_mmc_clk>;
> > > clk-gate = <0xa0 8>;
> > > + clk-phase = <0 135>;
> >
> > Can clk-phase be applicable commonly for various board?
> > Isn't specific timing values?
>
> No, the clock-phase does not change for various board. It is a
> SoC-specific property.
I'm curious about this: If the setting is fixed per soc, why is it even
configurable, rather than hardwired to the correct setting, or set up
by the boot loader?
Arnd
WARNING: multiple messages have this Message-ID (diff)
From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"
Date: Fri, 10 Jan 2014 20:00:25 +0100 [thread overview]
Message-ID: <201401102000.25484.arnd@arndb.de> (raw)
In-Reply-To: <1389369111.13556.29.camel@linux-builds1>
On Friday 10 January 2014, Dinh Nguyen wrote:
> > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > > index f936476..e776512 100644
> > > --- a/arch/arm/boot/dts/socfpga.dtsi
> > > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > > @@ -413,6 +413,7 @@
> > > compatible = "altr,socfpga-gate-clk";
> > > clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > > <&per_nand_mmc_clk>;
> > > clk-gate = <0xa0 8>;
> > > + clk-phase = <0 135>;
> >
> > Can clk-phase be applicable commonly for various board?
> > Isn't specific timing values?
>
> No, the clock-phase does not change for various board. It is a
> SoC-specific property.
I'm curious about this: If the setting is fixed per soc, why is it even
configurable, rather than hardwired to the correct setting, or set up
by the boot loader?
Arnd
next prev parent reply other threads:[~2014-01-10 19:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-09 21:31 [PATCHv9 0/4] socfpga: Enable SD/MMC support dinguyen
2014-01-09 21:31 ` dinguyen at altera.com
[not found] ` <1389303079-19808-1-git-send-email-dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
2014-01-09 21:31 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" dinguyen-EIB2kfCEclfQT0dZR+AlfA
2014-01-09 21:31 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" dinguyen at altera.com
2014-01-10 3:47 ` Jaehoon Chung
2014-01-10 3:47 ` Jaehoon Chung
2014-01-15 12:36 ` Dinh Nguyen
2014-01-15 12:36 ` Dinh Nguyen
2014-02-05 16:03 ` Mike Turquette
2014-02-05 16:03 ` Mike Turquette
2014-02-05 16:39 ` Dinh Nguyen
2014-02-05 16:39 ` Dinh Nguyen
2014-01-10 13:19 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" Seungwon Jeon
2014-01-10 13:19 ` Seungwon Jeon
2014-01-10 15:51 ` Dinh Nguyen
2014-01-10 15:51 ` Dinh Nguyen
2014-01-10 19:00 ` Arnd Bergmann [this message]
2014-01-10 19:00 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" Arnd Bergmann
2014-01-10 21:26 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" Dinh Nguyen
2014-01-10 21:26 ` [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" Dinh Nguyen
2014-01-09 21:31 ` [PATCHv9 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform dinguyen
2014-01-09 21:31 ` dinguyen at altera.com
2014-01-10 3:48 ` Jaehoon Chung
2014-01-10 3:48 ` Jaehoon Chung
2014-01-09 21:31 ` [PATCHv9 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc dinguyen
2014-01-09 21:31 ` dinguyen at altera.com
2014-01-10 3:48 ` Jaehoon Chung
2014-01-10 3:48 ` Jaehoon Chung
2014-01-09 21:31 ` [PATCHv9 4/4] ARM: socfpga_defconfig: enable SD/MMC support dinguyen
2014-01-09 21:31 ` dinguyen at altera.com
2014-01-10 3:49 ` Jaehoon Chung
2014-01-10 3:49 ` Jaehoon Chung
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